Christian Ulmann d8da5b5a09 [HandshakeToFIRRTL] Add initial values to buffer module names ... This commit adds the initial values to the names of the buffer modules to create different modules for different initial values.		2022-05-27 16:22:46 +02:00
..
Bindings	[MSFT] Tcl output: do not output `|` before subpath	2022-05-20 15:59:14 -07:00
Dialect	[HandshakeToFIRRTL] Add initial values to buffer module names	2022-05-27 16:22:46 +02:00
ESI	[llvm] Bump LLVM to latest main (#3132)	2022-05-20 20:05:53 +02:00
EmitVerilog	Update LLVM to 1aa4f0bb (#2901)	2022-04-15 16:07:46 -07:00
circt-rtl-sim	[Tests] Added Icarus Verilog test harness (#2739)	2022-03-26 10:21:20 +02:00
CMakeLists.txt	[Python] Re-work Python bindings using upstream improvements. (#1484)	2021-07-29 09:49:58 -06:00
lit.cfg.py	[Tests] Added Icarus Verilog test harness (#2739)	2022-03-26 10:21:20 +02:00
lit.site.cfg.py.in	[Tests] Added Icarus Verilog test harness (#2739)	2022-03-26 10:21:20 +02:00