..
AffineToStaticLogic
Fix SCF include paths. NFC.
2022-06-24 11:37:32 -07:00
CalyxToHW
[SV] Adopt prefixed accessors
2022-07-14 12:12:44 +02:00
ExportVerilog
[SV] Rename operation arguments to resolve ambiguities
2022-07-16 22:05:18 +02:00
FIRRTLToHW
[LowerToHW][FIRTOOL] Add an option to emit chisel asserts as sva ( #3545 )
2022-07-18 17:15:02 +09:00
FSMToSV
[FSMToSV] Use prefixed accessors
2022-07-16 22:15:55 +02:00
HWArithToHW
[HWArithToHW] Add lowering boilerplate ( #3546 )
2022-07-18 10:03:22 +02:00
HWToLLHD
[HW] Adopt prefixed accessors ( #3533 )
2022-07-14 11:08:23 +02:00
HandshakeToFIRRTL
[FIRRTL] Adopt prefixed accessors
2022-07-16 22:05:18 +02:00
HandshakeToHW
[CMakeLists] Match changes to upstream MLIR target names. NFC.
2022-06-24 11:37:32 -07:00
LLHDToLLVM
[Comb] Adopt prefixed accessors
2022-07-14 13:57:36 +02:00
MooreToCore
Update LLVM submodule ( #2928 )
2022-04-20 16:25:01 -07:00
SCFToCalyx
[CMakeLists] Match changes to upstream MLIR target names. NFC.
2022-06-24 11:37:32 -07:00
StandardToHandshake
[StandardToHandshake] Factor out the loop analysis ( #3436 )
2022-06-29 16:39:06 +02:00
StandardToStaticLogic
[CMakeLists] Match changes to upstream MLIR target names. NFC.
2022-06-24 11:37:32 -07:00
StaticLogicToCalyx
[CMakeLists] Match changes to upstream MLIR target names. NFC.
2022-06-24 11:37:32 -07:00
CMakeLists.txt
[HWArithToHW] Add lowering boilerplate ( #3546 )
2022-07-18 10:03:22 +02:00
PassDetail.h
[HWArithToHW] Add lowering boilerplate ( #3546 )
2022-07-18 10:03:22 +02:00