circt/integration_test
Morten Borup Petersen 041a5dc6a4 [PyCDE] Clarify BackedgeBuilder error message
Presumably, this error message stems from when BackedgeBuilder was initially used solely for creating backedges to top-level port assignments when creating a new module instance. However, the `BackedgeBuilder` is also used for other operations (and useful as a general tool), wherein 'port' may be misleading. Changing this to `Backedge` makes it explicit that a backedge was created, and was expected to be assigned to.
2022-07-18 15:21:52 +02:00
..
Bindings [PyCDE] Clarify BackedgeBuilder error message 2022-07-18 15:21:52 +02:00
Dialect [FSM] Use --no-default-driver in integration test 2022-07-18 11:03:52 +02:00
ESI [llvm] Bump LLVM to latest main (#3132) 2022-05-20 20:05:53 +02:00
EmitVerilog Update LLVM to 1aa4f0bb (#2901) 2022-04-15 16:07:46 -07:00
circt-rtl-sim [Tests] Added Icarus Verilog test harness (#2739) 2022-03-26 10:21:20 +02:00
CMakeLists.txt [Python] Re-work Python bindings using upstream improvements. (#1484) 2021-07-29 09:49:58 -06:00
lit.cfg.py [Tests] Added Icarus Verilog test harness (#2739) 2022-03-26 10:21:20 +02:00
lit.site.cfg.py.in [Tests] Added Icarus Verilog test harness (#2739) 2022-03-26 10:21:20 +02:00