mirror of https://github.com/llvm/circt.git
4c74e87023
Add an implementation of the SystemVerilog type system to the Moore dialect, modeled after the one in Moore's Rust codebase: https://github.com/fabianschuiki/moore/blob/master/src/svlog/ty.rs This is the first step towards migrating a larger chunk of the Moore codebase into CIRCT, as it allows Moore's codegen to start emitting higher-level operations (e.g., `moore.mir.concat`, to be added later) instead of directly dropping to LLHD/HW. Doing so will allow us to eventually move the codegen over into CIRCT, and start work on implementing the type checking and type inference on the higher-level operations. My hope is that we might eventually be able to reconcile the Moore types and some of the higher-level operations with the SV dialect, since both work with SystemVerilog, albeit for two diametrically opposed purposes. The types are designed to very clearly distinguish between packed and unpacked types, and provide a certain level of guarantees about the structure of nested types through C++ types. For example, struct aggregate types and typedefs/decltype constructs come in a packed and unpacked flavor to enforce proper nesting of these types. Where user-defined types are involved, for example through structs and typedefs/decltype, the MLIR types aim to capture enough information to faithfully reconstruct the type as it was originally formulated by the user. This helps provide good and understandable diagnostics. As a concrete example, integer types capture whether their sign was provided explicitly by the user, in order to distinguish `int` and `int signed`, despite those two types being semantically identical. This commit also adds a `unittests` directory as seen in LLVM and MLIR, to test the human-readable serialization of the Moore types and other type attributes. |
||
|---|---|---|
| .. | ||
| lit.cfg.py | ||
| lit.site.cfg.py.in | ||