circt/test
Schuyler Eldridge ae75dfa7a9
[FIRRTL] Rewrite Grand Central Views/Interfaces, Add XMR Support (#1496)
Rewrite the Grand Central Views/Interface pass to fully support the
Grand Central Chisel API.  Specifically, enable support for interfaces
that instantiate other interfaces, support n-dimensional vectors of
interfaces, and add generation of XMRs to drive the interfaces.

Change Grand Central annotation scattering to represent interfaces with
a recursive structure.  Interfaces which instantiate other interfaces
will show up as BundleTypes in the elements where they are instantiated.
This keeps the interface representation intact until the Grand Central
pass can choose to handle this however it wants.

Also, change scattering to using numeric IDs instead of relying on string
matching to keep track of interface membership.

Add an MLIR Attribute hierarchy to represent this recursive structure.
Use this to factor out verification logic from business logic that
generates interfaces.

After this rewrite, the pass now works in the following way:

1. Extraction information is pulled out from the circuit along with
   annotations that describe the interfaces.

2. The full circuit is walked to build up information about companions,
   parents, and leaves that will be connected to the interface.

3. Interface annotations on the circuit are then recursively walked to
   generate interfaces, instantiate interfaces, and generate XMRs in a
   "mappings" file that drives the interfaces.

A CircuitNamespace utility is added to generate unique symbols for
interfaces and binds that need to be created.

Interfaces (and other collateral) are only extracted if an
ExtractGrandCentralAnnotation is present.  This is a deviation from the
Scala FIRRTL Compiler Grand Central pass where absence of that
annotation will cause an assert to fire.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-09-08 01:55:23 -04:00
..
CAPI [llvm] Update submodule to latest (#1589) 2021-08-18 19:37:43 -07:00
Conversion LLVM Submodule Update (#1716) 2021-09-04 14:54:13 -07:00
Dialect [FIRRTL] Rewrite Grand Central Views/Interfaces, Add XMR Support (#1496) 2021-09-08 01:55:23 -04:00
ExportVerilog [ExportVerilog] Flip the default output of `sv.alwaysComb` ops (#1709) 2021-09-06 22:44:16 -07:00
Scheduling [Scheduling] [3/3] Add scheduler for shared pipelined operators problem: Heuristic algorithm. (#1622) 2021-08-23 22:15:06 +02:00
circt-opt [FSM] Add an empty FSM dialect (#1671) 2021-08-30 17:28:46 -05:00
circt-reduce [reduce] Add a first proof-of-concept reducer implementation with sample FIRRTL dialect reducers (#1591) 2021-08-18 17:22:43 +02:00
circt-translate Whitespace cleanup in test/ and *.td, NFC 2021-07-09 18:24:57 -04:00
firtool [ExportVerilog] Flip the default output of `sv.alwaysComb` ops (#1709) 2021-09-06 22:44:16 -07:00
handshake-runner [Handshake] Support handshake.InstanceOp in handshake-runner (#1542) 2021-08-27 16:53:04 +01:00
lib Partially revert #1688 in favor of style used in upstream MLIR (#1698) 2021-09-02 12:32:07 +01:00
verilator [Verilator] Make the error check more flexible (#264) 2020-11-20 11:37:13 -08:00
CMakeLists.txt Partially revert #1688 in favor of style used in upstream MLIR (#1698) 2021-09-02 12:32:07 +01:00
lit.cfg.py [reduce] Add a first proof-of-concept reducer implementation with sample FIRRTL dialect reducers (#1591) 2021-08-18 17:22:43 +02:00
lit.site.cfg.py.in Disable llhd-sim tests when the executable is not built (#1425) 2021-07-14 18:42:45 -04:00