John Demme 10180d3ca2 [ESI] Separate data delay from signaling standard (#7354) ... The control signaling is (for valid/ready and FIFO) orthogonal to the number of cycles data is delayed. Separate it out.		2024-07-23 16:37:25 -07:00
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Conversion	[LLHD] Use hw.inout instead of llhd.sig (#7353)	2024-07-19 20:51:33 +01:00
Dialect	[ESI] Separate data delay from signaling standard (#7354)	2024-07-23 16:37:25 -07:00
ExportFIRRTL	[CAPI] Add circt-capi target and build it in CI (#7017)	2024-05-09 11:21:33 -07:00
ExportVerilog	[CAPI] Add circt-capi target and build it in CI (#7017)	2024-05-09 11:21:33 -07:00
Firtool	[FIRRTL] Drop Hoistpassthroughs pass. (#7097)	2024-05-28 13:38:51 -05:00
CMakeLists.txt	[Firtool][CAPI] Add C-API for Firtool lib	2023-09-30 21:53:23 +08:00