mirror of https://github.com/llvm/circt.git
2e11065461
When a mux feeds an assign to a register and one branch of the mux is the register's old value, we can turn that into a conditional assign. This results in much cleaner verilog output. |
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| .. | ||
| build-llvm.sh | ||
| equiv-rtl.sh | ||
| get-capnp.sh | ||
| get-verilator.sh | ||
| run-docker.sh | ||
| run-tests-docker.sh | ||
| update-docs-dialects.sh | ||