John Demme 2174fb368c [MSFT] Support for multiple top levels of same module (#3321) ... Some designs instantiate the same module more than once. Per-instance data should be different, so we need a way to specify an "instance" of the top level		2022-06-10 16:49:41 -07:00
..
Analysis	LLVM bump (as we know it) (#3074)	2022-05-09 14:30:14 -07:00
CAPI	[llvm] Update submodule to latest (#1589)	2021-08-18 19:37:43 -07:00
Conversion	[LowerToHW] Disable threading in diagnostic tests; NFC	2022-06-10 16:06:40 +02:00
Dialect	[MSFT] Support for multiple top levels of same module (#3321)	2022-06-10 16:49:41 -07:00
Scheduling	LLVM bump (as we know it) (#3074)	2022-05-09 14:30:14 -07:00
Transforms	LLVM bump (as we know it) (#3074)	2022-05-09 14:30:14 -07:00
Unit	[Moore] Add SystemVerilog types (#2699)	2022-03-04 08:48:45 +01:00
circt-opt	LLVM bump (as we know it) (#3074)	2022-05-09 14:30:14 -07:00
circt-reduce	[FIRRTL] Split name preservation semantics into a dedicated attribute (#3247)	2022-06-09 16:59:36 +09:00
circt-translate	[LLHD] remove the LLHD-specific Verilog printer.	2021-12-08 14:01:45 -08:00
firtool	Revert "[FIRRTL] Cannonicalize wires to nodes (#3246)" (#3283)	2022-06-06 13:16:44 -06:00
handshake-runner	LLVM bump (as we know it) (#3074)	2022-05-09 14:30:14 -07:00
lib	[NFC] Added newlines to the end of files	2022-03-28 18:58:23 +03:00
llhd-sim	circt-reduce,firtool,llhd-sim: cleanup --help output, put options in category (#2979)	2022-05-03 16:02:57 -05:00
CMakeLists.txt	[FIRRTL] Fix black box directory from GCT	2022-03-25 01:32:57 -04:00
lit.cfg.py	[Scheduling] Set up infrastructure for using OR-Tools' solvers. (#2465)	2022-01-18 10:55:15 +01:00
lit.site.cfg.py.in	[Scheduling] Set up infrastructure for using OR-Tools' solvers. (#2465)	2022-01-18 10:55:15 +01:00