mirror of https://github.com/llvm/circt.git
5c7d2d81d9
We do this by analyzing how a portref is used inside a container, and then creating an in- or output port based on that. That is: - write to `portref<in portref<in, T>>` becomes `out T` i.e this container wants to write to an input of another container, hence it will produce an output value that will drive that input port. - read from `portref<in portref<out, T>>` becomes `in T` i.e. this container wants to read from an output of another container, hence it will have an input port that will be driven by that output port. - write to `portref<out portref<out, T>>` becomes `out T` i.e. a port reference inside the module will be driven by a value from the outside. - read from `portref<out portref<in, T>>` becomes `in T` i.e. a port reference inside the module will be driven by a value from the outside. A benefit of having portref lowering separate from portref tunneling is that portref lowering can be done on an `ibis.container` granularity, allowing for a bit of parallelism in the flow. |
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CommandGuide | ||
Dialects | ||
PyCDE | ||
includes | ||
CMakeLists.txt | ||
Charter.md | ||
GettingStarted.md | ||
HLS.md | ||
Passes.md | ||
PythonBindings.md | ||
RationaleSymbols.md | ||
Scheduling.md | ||
ToolsWorkarounds.md | ||
VerilogGeneration.md | ||
dialects.dot | ||
dialects.drawio | ||
doxygen-mainpage.dox | ||
doxygen.cfg.in |