mirror of https://github.com/llvm/circt.git
fc831b8f8b
Add indexed part-select op to the SV dialect. Added two ops named `sv.part_select` and `sv.part_select_inout`, that is lowered to the `indexed part-select` operation in SystemVerilog. The `sv.part_select` is defined on `Integer` type input and `sv.part_select_inout` is defined on `inout` type. Part-select consists of 3 arguments, the input value, a `width` and a `base` and an optional boolean attribute `decrement`. The `width` shall be a compile-time constant expression. The `base` can be a runtime integer expression. The operation selects bits starting at the `base` and ascending or descending the bit range. The number of bits selected is equal to the `width` expression. The bit addressing is always ascending starting from the `base`, unless the `decrement` attribute is specified. Part-select is defined in section 11.5.1 of 1800-2017 spec. |
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| .. | ||
| CommandGuide | ||
| Dialects | ||
| ESI | ||
| includes | ||
| CMakeLists.txt | ||
| Charter.md | ||
| FIRRTLAnnotations.md | ||
| GettingStarted.md | ||
| Passes.md | ||
| PyCDE.md | ||
| PythonBindings.md | ||
| RationaleComb.md | ||
| RationaleESI.md | ||
| RationaleFIRRTL.md | ||
| RationaleFSM.md | ||
| RationaleHW.md | ||
| RationaleSV.md | ||
| RationaleSeq.md | ||
| VerilogGeneration.md | ||
| dialects.drawio | ||
| doxygen-mainpage.dox | ||
| doxygen.cfg.in | ||