mirror of https://github.com/llvm/circt.git
44 lines
1.6 KiB
Plaintext
44 lines
1.6 KiB
Plaintext
; RUN: firtool %s --add-companion-assume --split-input-file | FileCheck %s
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FIRRTL version 4.0.0
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; CHECK-LABEL: module UnrOnly(
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circuit UnrOnly:
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public module UnrOnly:
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input clock : Clock
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input pred : UInt<1>
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input en : UInt<1>
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; CHECK: `ifdef USE_UNR_ONLY_CONSTRAINTS
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; CHECK-NEXT: assert property (@(posedge clock) ~en | pred);
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; CHECK-NEXT: `endif // USE_UNR_ONLY_CONSTRAINTS
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; CHECK-NEXT: `ifdef USE_PROPERTY_AS_CONSTRAINT
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; CHECK-NEXT: `ifdef USE_UNR_ONLY_CONSTRAINTS
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; CHECK-NEXT: wire _GEN = ~en | pred;
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; CHECK-NEXT: always @(edge _GEN)
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; CHECK-NEXT: assume(_GEN);
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; CHECK-NEXT: `endif // USE_UNR_ONLY_CONSTRAINTS
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; CHECK-NEXT: `endif // USE_PROPERTY_AS_CONSTRAINT
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intrinsic(circt_chisel_assert<guards="USE_UNR_ONLY_CONSTRAINTS">, clock, pred, en)
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;// -----
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FIRRTL version 4.0.0
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; CHECK-LABEL: module UnrOnlyLabel(
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circuit UnrOnlyLabel:
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public module UnrOnlyLabel:
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input clock : Clock
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input pred : UInt<1>
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input en : UInt<1>
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; CHECK: `ifdef USE_UNR_ONLY_CONSTRAINTS
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; CHECK-NEXT: assert__test: assert property (@(posedge clock) ~en | pred);
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; CHECK-NEXT: `endif // USE_UNR_ONLY_CONSTRAINTS
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; CHECK-NEXT: `ifdef USE_PROPERTY_AS_CONSTRAINT
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; CHECK-NEXT: `ifdef USE_UNR_ONLY_CONSTRAINTS
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; CHECK-NEXT: wire _GEN = ~en | pred;
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; CHECK-NEXT: always @(edge _GEN)
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; CHECK-NEXT: assume__test: assume(_GEN);
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; CHECK-NEXT: `endif // USE_UNR_ONLY_CONSTRAINTS
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; CHECK-NEXT: `endif // USE_PROPERTY_AS_CONSTRAINT
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intrinsic(circt_chisel_assert<guards="USE_UNR_ONLY_CONSTRAINTS", label="test">, clock, pred, en)
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