mirror of https://github.com/llvm/circt.git
40 lines
1.4 KiB
Plaintext
40 lines
1.4 KiB
Plaintext
; RUN: firtool %s | FileCheck %s
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FIRRTL version 4.0.0
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circuit Foo: %[[{"class": "firrtl.AttributeAnnotation",
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"description": "keep_hierarchy = \"true\"",
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"target": "~Foo|Foo"},
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{"class": "firrtl.AttributeAnnotation",
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"description": "mark_debug = \"yes\"",
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"target": "~Foo|Foo>w"},
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{"class": "firrtl.transforms.DontTouchAnnotation",
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"target": "~Foo|Foo>w"},
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{"class": "firrtl.AttributeAnnotation",
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"description": "mark_debug = \"yes\"",
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"target": "~Foo|Foo>n"},
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{"class": "firrtl.transforms.DontTouchAnnotation",
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"target": "~Foo|Foo>n"},
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{"class": "firrtl.AttributeAnnotation",
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"description": "keep = \"true\"",
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"target": "~Foo|Foo>r"}]]
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; CHECK: (* keep_hierarchy = "true" *)
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; CHECK-NEXT: module Foo
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public module Foo:
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input a: UInt<1>
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input clock: Clock
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output b1: UInt<1>
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output b2: UInt<1>
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; CHECK: (* mark_debug = "yes" *)
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; CHECK-NEXT: wire w
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wire w: UInt<1>
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; CHECK: (* mark_debug = "yes" *)
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; CHECK-NEXT: wire n
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node n = w;
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; CHECK: (* keep = "true" *)
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; CHECK-NEXT: reg r
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reg r: UInt<1>, clock
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connect w, a
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connect b1, n
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connect r, a
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connect b2, r
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