mirror of https://github.com/llvm/circt.git
121 lines
3.6 KiB
MLIR
121 lines
3.6 KiB
MLIR
// RUN: firtool %s --format=mlir -verilog | FileCheck %s --check-prefix=VERILOG
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// RUN: rm -rf %t
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// RUN: firtool %s --format=mlir -split-verilog -o=%t
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// RUN: FileCheck %s --check-prefix=VERILOG-FOO < %t/foo.sv
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// RUN: FileCheck %s --check-prefix=VERILOG-BAR < %t/bar.sv
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// RUN: FileCheck %s --check-prefix=VERILOG-USB < %t/usb.sv
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// RUN: FileCheck %s --check-prefix=VERILOG-INOUT-3 < %t/inout_3.sv
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// RUN: FileCheck %s --check-prefix=VERILOG-CUSTOM-1 < %t/custom1.sv
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// RUN: FileCheck %s --check-prefix=VERILOG-CUSTOM-2 < %t/custom2.sv
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// RUN: FileCheck %s --check-prefix=LIST < %t/filelist.f
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sv.verbatim "// I'm everywhere"
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sv.macro.decl @VERILATOR
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sv.ifdef @VERILATOR {
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sv.verbatim "// Hello"
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} else {
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sv.verbatim "// World"
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}
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sv.verbatim ""
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hw.type_scope @__hw_typedecls {
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hw.typedecl @foo : i1
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}
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hw.module @foo(in %a: i1, out b : i1) {
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hw.output %a : i1
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}
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hw.module @bar(in %x : i1, out y : i1) {
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hw.output %x : i1
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}
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sv.interface @usb {
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sv.interface.signal @valid : i1
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sv.interface.signal @ready : i1
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}
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hw.module.extern @pll ()
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hw.module @inout(in %inout: i1, out out : i1) {
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hw.output %inout : i1
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}
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// This is made to collide with the first renaming attempt of the `@inout`
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// module above.
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hw.module.extern @inout_0 ()
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hw.module.extern @inout_1 ()
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hw.module.extern @inout_2 ()
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sv.verbatim "// Foo" {output_file = #hw.output_file<"custom1.sv">}
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sv.verbatim "// Bar" {output_file = #hw.output_file<"custom2.sv", excludeFromFileList>}
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// LIST: {{^}}foo.sv{{$}}
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// LIST-NEXT: {{^}}bar.sv{{$}}
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// LIST-NEXT: {{^}}usb.sv{{$}}
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// LIST-NEXT: {{^}}inout_3.sv{{$}}
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// LIST-NEXT: {{^}}custom1.sv{{$}}
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// LIST-NOT: custom2.sv
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// VERILOG-FOO: // I'm everywhere
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// VERILOG-FOO-NEXT: `ifdef VERILATOR
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// VERILOG-FOO-NEXT: // Hello
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// VERILOG-FOO-NEXT: `else
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// VERILOG-FOO-NEXT: // World
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// VERILOG-FOO-NEXT: `endif
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// VERILOG-FOO: typedef logic foo;
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// VERILOG-FOO-LABEL: module foo(
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// VERILOG-FOO: endmodule
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// VERILOG-BAR: // I'm everywhere
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// VERILOG-BAR-NEXT: `ifdef VERILATOR
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// VERILOG-BAR-NEXT: // Hello
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// VERILOG-BAR-NEXT: `else
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// VERILOG-BAR-NEXT: // World
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// VERILOG-BAR-NEXT: `endif
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// VERILOG-BAR: typedef logic foo;
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// VERILOG-BAR-LABEL: module bar
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// VERILOG-BAR: endmodule
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// VERILOG-USB: // I'm everywhere
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// VERILOG-USB-NEXT: `ifdef VERILATOR
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// VERILOG-USB-NEXT: // Hello
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// VERILOG-USB-NEXT: `else
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// VERILOG-USB-NEXT: // World
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// VERILOG-USB-NEXT: `endif
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// VERILOG-USB: typedef logic foo;
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// VERILOG-USB-LABEL: interface usb;
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// VERILOG-USB: endinterface
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// VERILOG-INOUT-3: // I'm everywhere
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// VERILOG-INOUT-3-NEXT: `ifdef VERILATOR
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// VERILOG-INOUT-3-NEXT: // Hello
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// VERILOG-INOUT-3-NEXT: `else
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// VERILOG-INOUT-3-NEXT: // World
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// VERILOG-INOUT-3-NEXT: `endif
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// VERILOG-INOUT-3: typedef logic foo;
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// VERILOG-INOUT-3-LABEL: module inout_3(
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// VERILOG-INOUT-3: endmodule
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// VERILOG-CUSTOM-1: // Foo
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// VERILOG-CUSTOM-2: // Bar
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// VERILOG: // I'm everywhere
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// VERILOG-NEXT: `ifdef VERILATOR
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// VERILOG-NEXT: // Hello
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// VERILOG-NEXT: `else
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// VERILOG-NEXT: // World
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// VERILOG-NEXT: `endif
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// VERILOG: typedef logic foo;
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// VERILOG-LABEL: module foo(
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// VERILOG: endmodule
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// VERILOG-LABEL: module bar
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// VERILOG: endmodule
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// VERILOG-LABEL: interface usb;
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// VERILOG: endinterface
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// VERILOG-NOT: module pll
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// VERILOG-NOT: module inout_0
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// VERILOG-NOT: module inout_1
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// VERILOG-NOT: module inout_2
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// VERILOG-LABEL: FILE "custom1.sv"
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// VERILOG: // Foo
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// VERILOG-LABEL: FILE "custom2.sv"
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// VERILOG: // Bar
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