mirror of https://github.com/llvm/circt.git
20 lines
460 B
Plaintext
20 lines
460 B
Plaintext
; RUN: firtool %s
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; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
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FIRRTL version 3.0.0
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circuit Foo :
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module Foo :
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output p : Probe<{a: UInt, b: UInt}>
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; ...
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wire x : {a: UInt<5>, b: UInt<2>} ; XXX: ADDED
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invalidate x ; XXX: ADDED
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define p = probe(x) ; XXX: ADDED
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module Bar :
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output x : UInt
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inst f of Foo
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; SPEC EXAMPLE BEGIN
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connect x, add(read(f.p).a, read(f.p.b))
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; SPEC EXAMPLE END
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