mirror of https://github.com/llvm/circt.git
38 lines
908 B
Plaintext
38 lines
908 B
Plaintext
; RUN: firtool %s
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; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
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FIRRTL version 3.0.0
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circuit ForceAndRelease:
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; SPEC EXAMPLE BEGIN
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module ForceAndRelease:
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output o : UInt<3>
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inst r of AddRefs
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connect o, r.sum
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force_initial(r.a, UInt<2>(0))
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force_initial(r.a, UInt<2>(1))
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force_initial(r.b, UInt<2>(2))
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force_initial(r.c, UInt<2>(3))
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release_initial(r.c)
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; SPEC EXAMPLE END
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; include "force_addrefs.fir"
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module AddRefs:
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output a : RWProbe<UInt<2>>
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output b : RWProbe<UInt<2>>
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output c : RWProbe<UInt<2>>
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output sum : UInt<3>
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; XXX: modified, workaround inability create non-const node w/literal initializer.
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wire w : UInt<2>
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connect w, UInt<2>(0)
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node x = w
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node y = w
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node z = w
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connect sum, add(x, add(y, z))
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define a = rwprobe(x)
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define b = rwprobe(y)
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define c = rwprobe(z)
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