mirror of https://github.com/llvm/circt.git
16 lines
1.1 KiB
Plaintext
16 lines
1.1 KiB
Plaintext
; Ensure firtool can dump MLIR from various points of the pipeline.
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; Check passes from different components and registration categories.
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; RUN: firtool %s -mlir-print-ir-before=cse 2>&1 | FileCheck %s -Dpass=CSE
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; RUN: firtool %s -mlir-print-ir-before=firrtl-inliner 2>&1 | FileCheck %s -Dpass=Inliner
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; RUN: firtool %s -mlir-print-ir-before=firrtl-lower-annotations 2>&1 | FileCheck %s -Dpass=LowerFIRRTLAnnotations
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; RUN: firtool %s -mlir-print-ir-before=firrtl-grand-central 2>&1 | FileCheck %s -Dpass=GrandCentral
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; RUN: firtool %s -mlir-print-ir-before=export-verilog 2>&1 | FileCheck %s -Dpass=ExportVerilog
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; RUN: firtool %s -mlir-print-ir-before=export-split-verilog -split-verilog -o %t 2>&1 | FileCheck %s -Dpass=ExportSplitVerilog
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; RUN: firtool %s -mlir-print-ir-before=hw-cleanup 2>&1 | FileCheck %s -Dpass=HWCleanup
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; RUN: firtool %s -mlir-print-ir-before=lower-firrtl-to-hw 2>&1 | FileCheck %s -Dpass=LowerFIRRTLToHW
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; RUN: firtool %s -mlir-print-ir-before=prepare-for-emission 2>&1 | FileCheck %s -Dpass=PrepareForEmission
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; CHECK: IR Dump Before [[pass]]
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FIRRTL version 4.0.0
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circuit Empty:
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public module Empty:
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