mirror of https://github.com/llvm/circt.git
56 lines
1.6 KiB
Plaintext
56 lines
1.6 KiB
Plaintext
; RUN: firtool %s --format=fir --ir-fir | FileCheck %s
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; Temporary wires should not be introduced by type lowering, and if they are,
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; they should be cleaned up by canonicalize.
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; CHECK-LABEL: firrtl.module @Issue794
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; CHECK-SAME: (in %clock: !firrtl.clock,
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; CHECK: %[[memory_0:.+]] = firrtl.reg %clock {{.*}}: !firrtl.clock, !firrtl.uint<8>
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; CHECK: firrtl.mux(%[[v14:.+]], %wData_0, %[[memory_0]])
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; CHECK: firrtl.mux(%[[v19:.+]], %wData_1, %[[v5:.+]])
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; CHECK: firrtl.matchingconnect %[[memory_0]], %[[v22:.+]]
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FIRRTL version 4.0.0
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circuit Issue794: %[[{
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"class": "sifive.enterprise.firrtl.MarkDUTAnnotation",
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"target":"~Issue794|Issue794"
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},
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{
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"class": "sifive.enterprise.firrtl.ConvertMemToRegOfVecAnnotation$"
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}]]
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public module Issue794:
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input clock: Clock
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input rAddr: UInt<2>
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input rEn: UInt<1>
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output rData: UInt<8>
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input wAddr: UInt<2>[2]
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input wEn: UInt<1>[2]
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input wMask: UInt<1>[2]
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input wData: UInt<8>[2]
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mem memory:
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data-type => UInt<8>
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depth => 4
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reader => r
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writer => w0
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writer => w1
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read-latency => 0
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write-latency => 1
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read-under-write => undefined
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connect memory.r.clk, clock
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connect memory.r.en, rEn
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connect memory.r.addr, rAddr
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connect rData, memory.r.data
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connect memory.w0.clk, clock
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connect memory.w0.en, wEn[0]
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connect memory.w0.addr, wAddr[0]
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connect memory.w0.mask, wMask[0]
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connect memory.w0.data, wData[0]
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connect memory.w1.clk, clock
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connect memory.w1.en, wEn[1]
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connect memory.w1.addr, wAddr[1]
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connect memory.w1.mask, wMask[1]
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connect memory.w1.data, wData[1]
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