mirror of https://github.com/llvm/circt.git
130 lines
3.3 KiB
Plaintext
130 lines
3.3 KiB
Plaintext
; RUN: firtool %s --format=fir --annotation-file %s.anno.json --verilog | FileCheck %s
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; XFAIL: true
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FIRRTL version 4.0.0
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circuit test:
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module memoryTest1:
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input clock: Clock
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input rAddr: UInt<4>
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input rEn: UInt<1>
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output rData: UInt<8>
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input wMask: UInt<1>
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input wData: UInt<8>
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mem memory:
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data-type => UInt<8>
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depth => 16
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reader => r
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writer => w
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read-latency => 1
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write-latency => 1
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read-under-write => undefined
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; All of these are unified together
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connect memory.r.clk, clock
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connect memory.r.en, rEn
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connect memory.r.addr, rAddr
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connect rData, memory.r.data
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connect memory.w.clk, clock
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connect memory.w.en, rEn
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connect memory.w.addr, rAddr
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; These two are split
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connect memory.w.mask, wMask
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connect memory.w.data, wData
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module memoryTest2:
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input clock: Clock
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input rAddr: UInt<4>
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input rEn: UInt<1>
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output rData: UInt<8>
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input wMask: UInt<1>
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input wData: UInt<8>
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mem memory:
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data-type => UInt<8>
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depth => 16
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reader => r
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writer => w
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read-latency => 1
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write-latency => 1
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read-under-write => undefined
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; All of these are unified together
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connect memory.r.clk, clock
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connect memory.r.en, rEn
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connect memory.r.addr, rAddr
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connect rData, memory.r.data
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connect memory.w.clk, clock
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connect memory.w.en, rEn
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connect memory.w.addr, rAddr
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; These two are split
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connect memory.w.mask, wMask
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connect memory.w.data, wData
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public module test:
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input clock: Clock
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input rAddr: UInt<4>
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input rEn: UInt<1>
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output rData: UInt<8>
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input wMask: UInt<1>
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input wData: UInt<8>
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inst m of memoryTest1
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connect m.clock, clock
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connect m.rAddr, rAddr
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connect m.rEn, rEn
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connect rData, m.rData
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connect m.wMask, wMask
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connect m.wData, wData
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inst signed of memoryP
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connect signed.clock, clock
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connect signed.rAddr, rAddr
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connect signed.rEn, rEn
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connect rData, signed.rData
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connect signed.wMask, wMask
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connect signed.wData, wData
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module memoryP:
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input clock: Clock
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input rAddr: UInt<4>
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input rEn: UInt<1>
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output rData: UInt<8>
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input wMask: UInt<1>
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input wData: UInt<8>
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inst m of memoryTest2
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connect m.clock, clock
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connect m.rAddr, rAddr
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connect m.rEn, rEn
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connect rData, m.rData
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connect m.wMask, wMask
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connect m.wData, wData
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; CHECK-LABEL: module test
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; CHECK: memoryP [[signed:.+]] (
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; CHECK-LABEL: module memoryP
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; CHECK: memoryTest2 [[m:.+]] (
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; CHECK: FILE "metadata/tb_seq_mems.json"
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; CHECK: [{"module_name":"memory","depth":16,"width":8,"masked":"true",
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; CHECK-SAME: "read":"true","write":"true","readwrite":"false",
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; CHECK-SAME: "mask_granularity":8,"extra_ports":[],
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; CHECK-SAME: "hierarchy":["test.[[m]]"]}]
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; CHECK: FILE "metadata/seq_mems.json"
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; CHECK: [{"module_name":"memory","depth":16,"width":8,"masked":"true",
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; CHECK-SAME: "read":"true","write":"true","readwrite":"false",
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; CHECK-SAME: "mask_granularity":8,"extra_ports":[],
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; CHECK-SAME: "hierarchy":["test.[[signed]].[[m]]"],
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; CHECK-SAME: "verification_only_data":{
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; CHECK-SAME: "test.[[signed]].[[m]]":{"baseAddress":1073741824,
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; CHECK-SAME: "dataBits":8,"eccBits":0,"eccIndices":[],"eccScheme":"none"}}}]
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