mirror of https://github.com/llvm/circt.git
201 lines
4.9 KiB
Plaintext
201 lines
4.9 KiB
Plaintext
; RUN: firtool %s --annotation-file %s.anno.json --repl-seq-mem --repl-seq-mem-file="dutModule.conf" | FileCheck %s
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FIRRTL version 4.0.0
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circuit test:
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module tbMemModule1:
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input clock: Clock
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input rAddr: UInt<4>
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input rEn: UInt<1>
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output rData: UInt<8>
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input wMask: UInt<1>
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input wData: UInt<8>
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mem tbMemoryKind1:
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data-type => UInt<1>
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depth => 16
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reader => r
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writer => w
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read-latency => 1
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write-latency => 1
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read-under-write => undefined
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connect tbMemoryKind1.r.clk, clock
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connect tbMemoryKind1.r.en, rEn
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connect tbMemoryKind1.r.addr, rAddr
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connect rData, tbMemoryKind1.r.data
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connect tbMemoryKind1.w.clk, clock
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connect tbMemoryKind1.w.en, rEn
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connect tbMemoryKind1.w.addr, rAddr
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connect tbMemoryKind1.w.mask, wMask
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connect tbMemoryKind1.w.data, wData
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; CHECK-LABEL: module tbMemModule1
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; CHECK: tbMemoryKind1 tbMemoryKind1
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; CHECK: endmodule
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module dutModule2:
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input clock: Clock
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input rAddr: UInt<4>
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input rEn: UInt<1>
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output rData: UInt<8>
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input wMask: UInt<1>
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input wData: UInt<8>
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mem dutMemory:
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data-type => UInt<2>
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depth => 32
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reader => r
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writer => w
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read-latency => 1
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write-latency => 1
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read-under-write => undefined
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connect dutMemory.r.clk, clock
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connect dutMemory.r.en, rEn
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connect dutMemory.r.addr, rAddr
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connect rData, dutMemory.r.data
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connect dutMemory.w.clk, clock
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connect dutMemory.w.en, rEn
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connect dutMemory.w.addr, rAddr
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connect dutMemory.w.mask, wMask
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connect dutMemory.w.data, wData
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; CHECK-LABEL: module dutModule2
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; CHECK: dutMemory dutMemory
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module hier1:
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input clock: Clock
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input rAddr: UInt<4>
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input rEn: UInt<1>
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output rData: UInt<8>
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input wMask: UInt<1>
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input wData: UInt<8>
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mem tbMemoryKind1:
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data-type => UInt<3>
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depth => 16
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reader => r
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writer => w
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read-latency => 1
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write-latency => 1
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read-under-write => undefined
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connect tbMemoryKind1.r.clk, clock
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connect tbMemoryKind1.r.en, rEn
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connect tbMemoryKind1.r.addr, rAddr
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connect rData, tbMemoryKind1.r.data
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connect tbMemoryKind1.w.clk, clock
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connect tbMemoryKind1.w.en, rEn
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connect tbMemoryKind1.w.addr, rAddr
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connect tbMemoryKind1.w.mask, wMask
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connect tbMemoryKind1.w.data, wData
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; CHECK-LABEL: module hier1
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; CHECK: tbMemoryKind1_0 tbMemoryKind1
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module hier2:
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input clock: Clock
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input rAddr: UInt<4>
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input rEn: UInt<1>
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output rData: UInt<8>
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input wMask: UInt<1>
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input wData: UInt<8>
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inst m of tbMemModule1
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connect m.clock, clock
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connect m.rAddr, rAddr
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connect m.rEn, rEn
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connect rData, m.rData
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connect m.wMask, wMask
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connect m.wData, wData
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public module test:
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input clock: Clock
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input rAddr: UInt<4>
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input rEn: UInt<1>
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output rData: UInt<8>[3]
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input wMask: UInt<1>
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input wData: UInt<8>
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inst h1 of hier1
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connect h1.clock, clock
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connect h1.rAddr, rAddr
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connect h1.rEn, rEn
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connect rData[0], h1.rData
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connect h1.wMask, wMask
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connect h1.wData, wData
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inst h2 of hier2
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connect h2.clock, clock
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connect h2.rAddr, rAddr
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connect h2.rEn, rEn
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connect rData[1], h2.rData
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connect h2.wMask, wMask
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connect h2.wData, wData
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inst m2 of dutModule
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connect m2.clock, clock
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connect m2.rAddr, rAddr
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connect m2.rEn, rEn
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connect rData[2], m2.rData
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connect m2.wMask, wMask
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connect m2.wData, wData
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; CHECK-LABEL: module test
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; CHECK: hier1 [[h1:.+]] (
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; CHECK: hier2 [[h2:.+]] (
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; CHECK: dutModule [[m2:.+]] (
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module dutModule:
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input clock: Clock
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input rAddr: UInt<4>
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input rEn: UInt<1>
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output rData: UInt<8>
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input wMask: UInt<1>
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input wData: UInt<8>
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inst m of dutModule2
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connect m.clock, clock
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connect m.rAddr, rAddr
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connect m.rEn, rEn
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connect rData, m.rData
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connect m.wMask, wMask
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connect m.wData, wData
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; CHECK-LABEL: module dutModule
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; CHECK: dutModule2 [[m:.+]] (
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; CHECK-NOT: module tbMemoryKind1_ext
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; CHECK-NOT: module dutMemory_ext
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; CHECK-NOT: module tbMemoryKind1_0_ext
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; CHECK-LABEL: FILE "metadata{{[/\]}}seq_mems.json"
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; CHECK: [
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; CHECK-NEXT: {
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; CHECK-NEXT: "module_name": "dutMemory_ext",
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; CHECK-NEXT: "depth": 32,
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; CHECK-NEXT: "width": 2,
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; CHECK-NEXT: "masked": false,
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; CHECK-NEXT: "read": 1,
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; CHECK-NEXT: "write": 1,
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; CHECK-NEXT: "readwrite": 0,
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; CHECK-NEXT: "extra_ports": [],
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; CHECK-NEXT: "hierarchy": [
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; CHECK-NEXT: "dutModule.hello.dutMemory.dutMemory_ext"
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; CHECK-NEXT: ]
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; CHECK-NEXT: }
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; CHECK-NEXT: ]
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; CHECK-LABEL: FILE "dutModule.conf"
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; CHECK: name tbMemoryKind1_ext depth 16 width 1 ports write,read
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; CHECK: name dutMemory_ext depth 32 width 2 ports write,read
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; CHECK: name tbMemoryKind1_0_ext depth 16 width 3 ports write,read
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