mirror of https://github.com/llvm/circt.git
63 lines
1.6 KiB
Plaintext
63 lines
1.6 KiB
Plaintext
; RUN: firtool %s -repl-seq-mem -repl-seq-mem-file="test.conf" | FileCheck %s
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FIRRTL version 4.0.0
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circuit test: %[[
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{
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"class":"sifive.enterprise.firrtl.MarkDUTAnnotation",
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"target": "test.test"
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}
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]]
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public module test:
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input clock: Clock
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input rAddr: UInt<4>
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input rEn: UInt<1>
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output rData: UInt<8>[4]
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input wMask: UInt<1>[4]
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input wData: UInt<8>[4]
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mem memory:
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data-type => UInt<8>[4]
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depth => 16
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reader => r
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writer => w
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read-latency => 1
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write-latency => 1
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read-under-write => undefined
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; All of these are unified together
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connect memory.r.clk, clock
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connect memory.r.en, rEn
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connect memory.r.addr, rAddr
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connect rData, memory.r.data
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connect memory.w.clk, clock
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connect memory.w.en, rEn
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connect memory.w.addr, rAddr
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; These two are split
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connect memory.w.mask, wMask
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connect memory.w.data, wData
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; CHECK-NOT: module memory_ext
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; CHECK-LABEL: FILE "metadata{{[/\]}}seq_mems.json"
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; CHECK: [
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; CHECK-NEXT: {
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; CHECK-NEXT: "module_name": "memory_ext",
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; CHECK-NEXT: "depth": 16,
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; CHECK-NEXT: "width": 32,
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; CHECK-NEXT: "masked": true,
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; CHECK-NEXT: "read": 1,
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; CHECK-NEXT: "write": 1,
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; CHECK-NEXT: "readwrite": 0,
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; CHECK-NEXT: "mask_granularity": 8,
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; CHECK-NEXT: "extra_ports": [],
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; CHECK-NEXT: "hierarchy": [
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; CHECK-NEXT: "test.memory.memory_ext"
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; CHECK-NEXT: ]
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; CHECK-NEXT: }
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; CHECK-NEXT: ]
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; CHECK: test.conf
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; CHECK: name memory_ext depth 16 width 32 ports mwrite,read mask_gran 8
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