mirror of https://github.com/llvm/circt.git
129 lines
4.6 KiB
Plaintext
129 lines
4.6 KiB
Plaintext
; RUN: firtool %s --format=fir --ir-sv | FileCheck %s --check-prefixes=CHECK,COMMON --implicit-check-not sv.attributes
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; RUN: firtool %s --format=fir --ir-sv -disable-mem-randomization | FileCheck %s --check-prefix COMMON --implicit-check-not RANDOMIZE_MEM
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; RUN: firtool %s --format=fir --ir-sv -disable-reg-randomization | FileCheck %s --check-prefix COMMON --implicit-check-not RANDOMIZE_REG
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; RUN: firtool %s --format=fir --ir-sv -disable-mem-randomization --disable-reg-randomization | FileCheck %s --check-prefix COMMON --implicit-check-not RANDOMIZE_MEM --implicit-check-not RANDOMIZE_REG
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; RUN: firtool %s --format=fir --ir-sv -disable-all-randomization | FileCheck %s --check-prefix COMMON --implicit-check-not RANDOMIZE_MEM --implicit-check-not RANDOMIZE_REG
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FIRRTL version 4.0.0
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circuit Qux: %[[{
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"class": "sifive.enterprise.firrtl.MarkDUTAnnotation",
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"target":"~Qux|Qux"
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},
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{
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"class": "sifive.enterprise.firrtl.ConvertMemToRegOfVecAnnotation$"
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}]]
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public module Qux:
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input clock: Clock
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input rAddr: UInt<2>
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input rEn: UInt<1>
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output rData: UInt<8>
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input wAddr: UInt<2>
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input wEn: UInt<1>
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input wMask: UInt<1>
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input wData: UInt<8>
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input rwEn: UInt<1>
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input rwMode: UInt<1>
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input rwAddr: UInt<2>
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input rwMask: UInt<1>
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input rwDataIn: UInt<8>
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output rwDataOut: UInt<8>
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mem memory:
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data-type => UInt<8>
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depth => 4
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reader => r
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writer => w
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readwriter => rw
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read-latency => 1
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write-latency => 1
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read-under-write => undefined
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; All of these are unified together
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connect memory.r.clk, clock
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connect memory.r.en, rEn
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connect memory.r.addr, rAddr
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; This is split
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connect rData, memory.r.data
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; All of these are unified together
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connect memory.w.clk, clock
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connect memory.w.en, wEn
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connect memory.w.addr, wAddr
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; These two are split
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connect memory.w.mask, wMask
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connect memory.w.data, wData
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; All of these are unified together
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connect memory.rw.clk, clock
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connect memory.rw.en, rwEn
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connect memory.rw.addr, rwAddr
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connect memory.rw.wmode, rwMode
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; All of these are split
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connect memory.rw.wmask, rwMask
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connect memory.rw.wdata, rwDataIn
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connect rwDataOut, memory.rw.rdata
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; This test is quite fragile, both as written, and in that it depends on
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; multiple passes. It should be replaced with a narrower test.
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;COMMON-LABEL: hw.module @Qux
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;CHECK: %[[memory_0:.+]] = sv.reg
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;CHECK: %[[memory_1:.+]] = sv.reg
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;CHECK: %[[memory_2:.+]] = sv.reg
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;CHECK: %[[memory_3:.+]] = sv.reg
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;CHECK: %[[addr:.+]] = sv.reg
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;CHECK: %[[v4:.+]] = sv.read_inout %[[addr]]
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;CHECK: %[[v5:.+]] = hw.array_create
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;CHECK: %[[v6:.+]] = hw.array_get %[[v5]][%[[v4]]]
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;CHECK: %[[v7:.+]] = hw.array_get %[[v5]][%rwAddr]
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;CHECK: %8 = comb.icmp bin eq %rwAddr, %c0_i2 : i2
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;CHECK: %9 = comb.and bin %rwEn, %rwMode, %rwMask, %8 : i1
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;CHECK: %10 = comb.icmp bin eq %rwAddr, %c1_i2 : i2
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;CHECK: %11 = comb.and bin %rwEn, %rwMode, %rwMask, %10 : i1
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;CHECK: %12 = comb.icmp bin eq %rwAddr, %c-2_i2 : i2
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;CHECK: %13 = comb.and bin %rwEn, %rwMode, %rwMask, %12 : i1
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;CHECK: %14 = comb.icmp bin eq %rwAddr, %c-1_i2 : i2
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;CHECK: %15 = comb.and bin %rwEn, %rwMode, %rwMask, %14 : i1
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;CHECK: %16 = comb.icmp bin eq %wAddr, %c0_i2 : i2
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;CHECK: %17 = comb.and bin %wEn, %wMask, %16 : i1
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;CHECK: %18 = comb.icmp bin eq %wAddr, %c1_i2 : i2
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;CHECK: %19 = comb.and bin %wEn, %wMask, %18 : i1
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;CHECK: %20 = comb.icmp bin eq %wAddr, %c-2_i2 : i2
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;CHECK: %21 = comb.and bin %wEn, %wMask, %20 : i1
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;CHECK: %22 = comb.icmp bin eq %wAddr, %c-1_i2 : i2
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;CHECK: %23 = comb.and bin %wEn, %wMask, %22 : i1
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;CHECK: sv.always posedge %clock {
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;CHECK: sv.if %17 {
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;CHECK: sv.passign %memory_0, %wData : i8
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;CHECK: } else {
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;CHECK: sv.if %9 {
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;CHECK: sv.passign %memory_0, %rwDataIn : i8
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;CHECK: }
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;CHECK: }
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;CHECK: sv.if %19 {
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;CHECK: sv.passign %memory_1, %wData : i8
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;CHECK: } else {
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;CHECK: sv.if %11 {
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;CHECK: sv.passign %memory_1, %rwDataIn : i8
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;CHECK: }
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;CHECK: }
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;CHECK: sv.if %21 {
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;CHECK: sv.passign %memory_2, %wData : i8
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;CHECK: } else {
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;CHECK: sv.if %13 {
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;CHECK: sv.passign %memory_2, %rwDataIn : i8
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;CHECK: }
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;CHECK: }
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;CHECK: sv.if %23 {
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;CHECK: sv.passign %memory_3, %wData : i8
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;CHECK: } else {
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;CHECK: sv.if %15 {
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;CHECK: sv.passign %memory_3, %rwDataIn : i8
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;CHECK: }
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;CHECK: }
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;CHECK: sv.passign %addr, %rAddr : i2
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;CHECK: }
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;CHECK: hw.output %[[v6]], %[[v7]]
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