mirror of https://github.com/llvm/circt.git
30 lines
783 B
Plaintext
30 lines
783 B
Plaintext
; RUN: firtool %s -ir-verilog | FileCheck %s
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FIRRTL version 4.1.0
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; COM: Check that we can even target an extmodule.
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circuit Test : %[[
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{
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"class": "sifive.enterprise.firrtl.MarkDUTAnnotation",
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"target": "~Test|DUT"
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}
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]]
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; CHECK: hw.hierpath private [[DUT_NLA:@.+]] [@Test::[[DUT_SYM:@.+]]]
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public module Test :
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input in : UInt<1>
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output out : UInt<1>
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; CHECK: hw.instance "dut" sym [[DUT_SYM]]
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inst dut of DUT
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connect dut.in, in
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connect out, dut.out
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extmodule DUT :
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input in : UInt<1>
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output out : UInt<1>
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; COM: Check that metadata includes the dutModulePath pointing to Test::dut.
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; CHECK: om.class @SiFive_Metadata(%basepath: !om.basepath) -> (dutModulePath
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; CHECK-NEXT: om.path_create instance %basepath [[DUT_NLA]]
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