mirror of https://github.com/llvm/circt.git
81 lines
1.8 KiB
Plaintext
81 lines
1.8 KiB
Plaintext
; RUN: firtool %s --split-input-file | FileCheck %s
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; CHECK: Generated by
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; CHECK-LABEL: module TestHarness(
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FIRRTL version 4.0.0
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circuit TestHarness:
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extmodule DUT:
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input clock: Clock
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output read: Probe<UInt<32>>
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output write: RWProbe<UInt<32>>
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public module TestHarness:
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input clock: Clock
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inst dut of DUT
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connect dut.clock, clock
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; CHECK: fwrite
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; CHECK-SAME: "%x", TestHarness.dut.`ref_DUT_read)
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printf(clock, UInt<1>(1), "%x", read(dut.read))
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; CHECK: initial
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; CHECK: force TestHarness.dut.`ref_DUT_write = 32'hDEADBEEF;
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force_initial(dut.write, UInt<32>(0hdeadbeef))
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; CHECK: endmodule
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; // -----
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; CHECK: Generated by
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; CHECK-LABEL: module DUT(
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FIRRTL version 4.0.0
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circuit DUT:
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extmodule NotTheRealName:
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input clock: Clock
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output read: Probe<UInt<32>>
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output write: RWProbe<UInt<32>>
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defname = Inner
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public module DUT:
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input clock: Clock
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output read: Probe<UInt<32>>
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output write: RWProbe<UInt<32>>
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inst i of NotTheRealName
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connect i.clock, clock
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define read = i.read
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define write = i.write
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; CHECK-LABEL: FILE "ref_DUT.sv"
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; CHECK-EMPTY:
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; CHECK-NEXT: Generated by
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; CHECK-NEXT: `define ref_DUT_read i.`ref_Inner_read
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; CHECK-NEXT: `define ref_DUT_write i.`ref_Inner_write
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; // -----
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; CHECK: Generated by
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; CHECK-LABEL: module Inner(
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FIRRTL version 4.0.0
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circuit Inner:
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public module Inner:
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input clock: Clock
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output read: Probe<UInt<32>>
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output write: RWProbe<UInt<32>>
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reg r : UInt<32>, clock
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define read = probe(r)
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define write = rwprobe(r)
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; CHECK: reg [31:0] [[REG:.+]];
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; CHECK: wire [31:0] [[REG_READ:.+]] = [[REG]];
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; CHECK-LABEL: FILE "ref_Inner.sv"
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; CHECK-EMPTY:
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; CHECK-NEXT: Generated by
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; CHECK-NEXT: `define ref_Inner_read [[REG_READ]]
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; CHECK-NEXT: `define ref_Inner_write [[REG]]
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