mirror of https://github.com/llvm/circt.git
52 lines
2.4 KiB
MLIR
52 lines
2.4 KiB
MLIR
// RUN: firtool %s --format=mlir --ir-fir | circt-opt | FileCheck %s --check-prefix=MLIR
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// RUN: firtool %s --format=mlir --ir-fir --emit-bytecode | circt-opt | FileCheck %s --check-prefix=MLIR
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// RUN: circt-opt %s --emit-bytecode | firtool --ir-fir | circt-opt | FileCheck %s --check-prefix=MLIR
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// RUN: firtool %s --format=mlir -verilog | FileCheck %s --check-prefix=VERILOG
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// RUN: firtool %s --format=mlir -verilog -output-final-mlir=%t -output-hw-mlir=%t.hw.mlir | FileCheck %s --check-prefix=VERILOG-WITH-MLIR
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// RUN: firtool %s --format=mlir -verilog -output-final-mlir=%t.mlirbc -output-hw-mlir=%t.hw.mlirbc -emit-bytecode | FileCheck %s --check-prefix=VERILOG-WITH-MLIR
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// RUN: FileCheck %s --input-file=%t --check-prefix=VERILOG-WITH-MLIR-OUT
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// RUN: circt-opt %t.mlirbc | FileCheck %s --check-prefix=VERILOG-WITH-MLIR-OUT
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// RUN: not diff %t %t.mlirbc
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// RUN: FileCheck %s --input-file=%t.hw.mlir --check-prefix=VERILOG-WITH-HW-MLIR-OUT
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// RUN: circt-opt %t.hw.mlirbc | FileCheck %s --check-prefix=VERILOG-WITH-HW-MLIR-OUT
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// RUN: not diff %t.hw.mlir %t.hw.mlirbc
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firrtl.circuit "Top" {
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firrtl.module @Top(in %clock: !firrtl.clock, in %in : !firrtl.uint<8>,
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out %out : !firrtl.uint<8>) {
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firrtl.connect %out, %in : !firrtl.uint<8>, !firrtl.uint<8>
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}
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}
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// MLIR-LABEL: firrtl.module @Top(in %clock: !firrtl.clock, in %in: !firrtl.uint<8>, out %out: !firrtl.uint<8>) {
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// MLIR-NEXT: firrtl.matchingconnect %out, %in : !firrtl.uint<8>
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// MLIR-NEXT: }
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// VERILOG-LABEL: module Top(
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// VERILOG-NEXT: input clock,
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// VERILOG-NEXT: input [7:0] in,
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// VERILOG-NEXT: output [7:0] out
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// VERILOG-NEXT: );
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// VERILOG-EMPTY:
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// VERILOG-NEXT: assign out = in;
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// VERILOG-NEXT: endmodule
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// VERILOG-WITH-MLIR-LABEL: module Top(
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// VERILOG-WITH-MLIR-NEXT: input clock,
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// VERILOG-WITH-MLIR-NEXT: input [7:0] in,
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// VERILOG-WITH-MLIR-NEXT: output [7:0] out
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// VERILOG-WITH-MLIR-NEXT: );
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// VERILOG-WITH-MLIR-EMPTY:
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// VERILOG-WITH-MLIR-NEXT: assign out = in;
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// VERILOG-WITH-MLIR-NEXT: endmodule
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// VERILOG-WITH-MLIR-OUT-LABEL: hw.module @Top(in %clock : i1, in %in : i8, out out : i8) {
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// VERILOG-WITH-MLIR-OUT-NEXT: hw.output %in : i8
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// VERILOG-WITH-MLIR-OUT-NEXT: }
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// Check there is !seq.clock
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// VERILOG-WITH-HW-MLIR-OUT-LABEL: hw.module @Top(in %clock : !seq.clock, in %in : i8, out out : i8) {
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// VERILOG-WITH-HW-MLIR-OUT-NEXT: hw.output %in : i8
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// VERILOG-WITH-HW-MLIR-OUT-NEXT: }
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