mirror of https://github.com/llvm/circt.git
14 lines
693 B
MLIR
14 lines
693 B
MLIR
// RUN: firtool %s -format=mlir -verilog -verify-diagnostics | FileCheck --allow-empty %s
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firrtl.circuit "top" {
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// expected-error @below {{'firrtl.module' op contains a 'chisel3.util.experimental.ForceNameAnnotation' that is not a non-local annotation}}
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// expected-note @below {{the erroneous annotation is '{class = "chisel3.util.experimental.ForceNameAnnotation"}'}}
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// expected-warning @below {{module `top` is empty but cannot be removed because the module is public}}
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firrtl.module @top() attributes {annotations = [{class = "chisel3.util.experimental.ForceNameAnnotation"}]} {
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}
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}
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// Ensure circuits that error out don't make it to ExportVerilog.
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// CHECK-NOT: module top
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