mirror of https://github.com/llvm/circt.git
67 lines
1.8 KiB
Plaintext
67 lines
1.8 KiB
Plaintext
; RUN: firtool %s -extract-test-code | FileCheck %s
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; RUN: firtool %s -extract-test-code -etc-disable-instance-extraction | FileCheck %s --check-prefix=DISABLEINSTANCE
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; RUN: firtool %s -extract-test-code -etc-disable-module-inlining | FileCheck %s --check-prefix=DISABLEMODULE
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FIRRTL version 4.0.0
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circuit Top:
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module Foo:
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input a : UInt<1>
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output b : UInt<1>
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connect b, a
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; Ensure foo is extracted by default.
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; CHECK-LABEL: module InstanceExtracted_assert(
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; CHECK: Foo foo
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; Ensure foo is not extracted when disabled.
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; DISABLEINSTANCE-LABEL: module InstanceExtracted(
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; DISABLEINSTANCE: Foo foo
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module InstanceExtracted:
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input clock : Clock
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input cond : UInt<1>
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output out : UInt<1>
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wire b : UInt<1>
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inst foo of Foo
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connect foo.a, cond
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connect b, foo.b
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assert(clock, cond, b, "Some assertion")
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connect out, cond
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; Ensure InputOnly is inlined by default.
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; CHECK-NOT: module InputOnly(
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; Ensure InputOnly is not inlined when disabled.
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; DISABLEMODULE-LABEL: module InputOnly(
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module InputOnly:
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input clock : Clock
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input cond : UInt<1>
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assert(clock, cond, cond, "Some assertion")
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; CHECK: module Top_assert(
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; CHECK-NOT: endmodule
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; CHECK: wire _GEN = ~en;
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; CHECK: foo: assert property (disable iff (_GEN) cond);
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; CHECK: endmodule
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public module Top:
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input clock : Clock
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input cond : UInt<1>
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input en : UInt<1>
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output out : UInt<1>
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inst instance_extracted of InstanceExtracted
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connect instance_extracted.clock, clock
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connect instance_extracted.cond, cond
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connect out, instance_extracted.out
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inst input_only of InputOnly
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connect input_only.clock, clock
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connect input_only.cond, cond
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intrinsic(circt_verif_assert<label="foo">, cond, en)
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