mirror of https://github.com/llvm/circt.git
43 lines
1.1 KiB
Plaintext
43 lines
1.1 KiB
Plaintext
; RUN: rm -rf %t
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; RUN: firtool %s -split-verilog -o %t
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; RUN: cat %t/ref_Top.sv | FileCheck %s
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; CHECK: `define ref_Top_direct_probe _GEN{{(_[[0-9]+])?}}
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; CHECK-NEXT: `define ref_Top_inner_x_probe inner.x_probe
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; CHECK-NEXT: `define ref_Top_inner_y_probe _GEN{{(_[0-9]+])?}}
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; CHECK-NEXT: `define ref_Top_keyword_probe _GEN{{(_[[0-9]+])?}}
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FIRRTL version 3.0.0
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circuit Top: %[[
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{"class": "firrtl.transforms.DontTouchAnnotation", "target": "~Top|Inner>x"}
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]]
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module Top:
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output direct_probe: Probe<UInt<1>>
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output inner_x_probe: Probe<UInt<2>>
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output inner_y_probe: Probe<UInt<2>>
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output keyword_probe: Probe<UInt<3>>
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wire direct: UInt<1>
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invalidate direct
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define direct_probe = probe(direct)
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inst inner of Inner
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define inner_x_probe = inner.x_probe
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define inner_y_probe = inner.y_probe
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wire always: UInt<3>
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invalidate always
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define keyword_probe = probe(always)
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module Inner:
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output x_probe: Probe<UInt<2>>
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output y_probe: Probe<UInt<2>>
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wire x: UInt<2>
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invalidate x
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wire y : UInt<2>
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invalidate y
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define x_probe = probe(x)
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define y_probe = probe(y)
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