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; RUN: firtool %s | FileCheck %s
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FIRRTL version 4.0.0
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circuit Foo:
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public module Foo:
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input clk: Clock
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output inverted_clk: Clock
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connect inverted_clk, intrinsic(circt_clock_inv : Clock, clk)
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; CHECK-LABEL: module Foo
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; CHECK: assign inverted_clk = ~clk;
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