mirror of https://github.com/llvm/circt.git
26 lines
770 B
Plaintext
26 lines
770 B
Plaintext
; RUN: firtool %s | FileCheck %s --check-prefixes=CHECK,CHECK-DEFAULT
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; RUN: firtool %s --ckg-name=MyClockGate --ckg-input=CI --ckg-output=CO --ckg-enable=E --ckg-test-enable=TE | FileCheck %s --check-prefixes=CHECK,CHECK-CUSTOM
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FIRRTL version 4.0.0
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circuit Foo:
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public module Foo:
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input clk: Clock
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input enable: UInt<1>
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output gated_clk: Clock
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connect gated_clk, intrinsic(circt_clock_gate : Clock, clk, enable)
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; CHECK-LABEL: module Foo(
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; CHECK-DEFAULT: EICG_wrapper ckg (
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; CHECK-DEFAULT: .in (clk)
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; CHECK-DEFAULT: .out (gated_clk)
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; CHECK-DEFAULT: .en (enable)
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; CHECK-DEFAULT: .test_en (1'h0)
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; CHECK-CUSTOM: MyClockGate ckg (
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; CHECK-CUSTOM: .CI (clk)
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; CHECK-CUSTOM: .CO (gated_clk)
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; CHECK-CUSTOM: .E (enable)
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; CHECK-CUSTOM: .TE (1'h0)
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