mirror of https://github.com/llvm/circt.git
147 lines
4.0 KiB
Plaintext
147 lines
4.0 KiB
Plaintext
; RUN: firtool %s -ir-verilog | FileCheck %s
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FIRRTL version 4.2.0
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circuit Test : %[[
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{
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"class": "firrtl.transforms.MustDeduplicateAnnotation",
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"modules": ["~Test|CPU_1", "~Test|CPU_2"]
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}
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]]
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; CHECK: hw.hierpath private [[NLA1:@.+]] [@CPU_1::[[SYM1:@.+]]]
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; CHECK: hw.hierpath private [[NLA2:@.+]] [@CPU_1::[[SYM2:@.+]], @Fetch_1::[[SYM3:@.+]]]
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public module Test :
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input in : UInt<1>
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output out_1 : UInt<1>
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output out_2 : UInt<1>
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output om_out_1 : AnyRef
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output om_out_2 : AnyRef
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inst cpu_1 of CPU_1
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inst cpu_2 of CPU_2
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connect cpu_1.in, in
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connect cpu_2.in, in
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connect out_1, cpu_1.out
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connect out_2, cpu_2.out
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propassign om_out_1, cpu_1.om_out
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propassign om_out_2, cpu_2.om_out
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; CHECK-LABEL: hw.module private @CPU_1
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; CHECK-SAME: out out : i1 {hw.exportPort = #hw<innerSym[[SYM1]]>}
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module CPU_1 :
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input in : UInt<1>
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output out : UInt<1>
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output om_out : AnyRef
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object om of OM_1
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propassign om_out, om
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; CHECK: hw.instance "fetch_1" sym [[SYM2]]
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inst fetch_1 of Fetch_1
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inst fetch_2 of Fetch_1
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connect fetch_1.in, in
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connect fetch_2.in, in
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connect out, fetch_1.out
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; CHECK-NOT: CPU_2
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module CPU_2 :
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input in : UInt<1>
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output out : UInt<1>
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output om_out : AnyRef
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object om of OM_2
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propassign om_out, om
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inst fetch_1 of Fetch_2
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inst fetch_2 of Fetch_2
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connect fetch_1.in, in
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connect fetch_2.in, in
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connect out, fetch_1.out
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module Fetch_1 :
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input in : UInt<1>
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output out : UInt<1>
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; CHECK: %foo = sv.wire sym [[SYM3]]
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wire foo : UInt<1>
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connect foo, in
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connect out, foo
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; CHECK-NOT: Fetch_2
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module Fetch_2 :
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input in : UInt<1>
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output out : UInt<1>
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wire foo : UInt<1>
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connect foo, in
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connect out, foo
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class Foo_1 :
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output out_foo : Integer
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propassign out_foo, Integer(1)
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class Foo_2 :
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output out_bar : Integer
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propassign out_bar, Integer(1)
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class Foo_3 :
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output out_baz : Integer
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propassign out_baz, Integer(1)
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class Foo_4 :
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output out_baz : Integer
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propassign out_baz, Integer(1)
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; CHECK-LABEL: om.class @OM_1(%basepath: !om.basepath) -> (out_foo_1: !om.class.type<@Foo_1>, out_foo_2: !om.class.type<@Foo_2>, out_foo_3: !om.class.type<@Foo_3>, out_foo_4: !om.class.type<@Foo_3>, out_1: !om.path, out_2: !om.path)
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class OM_1 :
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output out_1 : Path
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output out_2 : Path
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output out_foo_1 : Inst<Foo_1>
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output out_foo_2 : Inst<Foo_2>
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output out_foo_3 : Inst<Foo_3>
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output out_foo_4 : Inst<Foo_4>
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; CHECK: [[FOO_1:%.+]] = om.object @Foo_1
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object foo_1 of Foo_1
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propassign out_foo_1, foo_1
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; CHECK: [[FOO_2:%.+]] = om.object @Foo_2
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object foo_2 of Foo_2
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propassign out_foo_2, foo_2
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; CHECK: [[FOO_3:%.+]] = om.object @Foo_3
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object foo_3 of Foo_3
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propassign out_foo_3, foo_3
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; CHECK: [[FOO_4:%.+]] = om.object @Foo_3
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object foo_4 of Foo_4
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propassign out_foo_4, foo_4
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; CHECK: om.path_create reference %basepath [[NLA1]]
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propassign out_1, path("OMReferenceTarget:~Test|CPU_1>out")
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; CHECK: om.path_create reference %basepath [[NLA2]]
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propassign out_2, path("OMReferenceTarget:~Test|CPU_1/fetch_1:Fetch_1>foo")
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; CHECK: om.class.fields [[FOO_1]], [[FOO_2]], [[FOO_3]], [[FOO_4]], %4, %5 : !om.class.type<@Foo_1>, !om.class.type<@Foo_2>, !om.class.type<@Foo_3>, !om.class.type<@Foo_3>, !om.path, !om.path
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; CHECK-NOT: OM_2
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class OM_2 :
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output out_1 : Path
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output out_2 : Path
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output out_foo_1 : Inst<Foo_1>
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output out_foo_2 : Inst<Foo_2>
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output out_foo_3 : Inst<Foo_3>
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output out_foo_4 : Inst<Foo_4>
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object foo_1 of Foo_1
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propassign out_foo_1, foo_1
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object foo_2 of Foo_2
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propassign out_foo_2, foo_2
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object foo_3 of Foo_3
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propassign out_foo_3, foo_3
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object foo_4 of Foo_4
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propassign out_foo_4, foo_4
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propassign out_1, path("OMReferenceTarget:~Test|CPU_2>out")
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propassign out_2, path("OMReferenceTarget:~Test|CPU_2/fetch_1:Fetch_2>foo")
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