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28 lines
915 B
Plaintext
28 lines
915 B
Plaintext
; Test exporting a Chisel interface to std-out.
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; RUN: firtool %s --disable-output --export-chisel-interface | FileCheck %s
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; Test exporting a Chisel interface to a directory.
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; RUN: firtool %s --disable-output --export-chisel-interface --chisel-interface-out-dir %t
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; RUN: FileCheck %s -input-file=%t/Foo.scala
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; Test exporting a Chisel interface to the default directory.
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; RUN: firtool %s --split-verilog --export-chisel-interface -o %t
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; RUN: FileCheck %s -input-file=%t/Foo.scala
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; CHECK-LABEL: // Generated by CIRCT
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; CHECK-LABEL: package shelf.foo
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; CHECK-LABEL: import chisel3._
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; CHECK-NEXT: import chisel3.experimental._
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; CHECK-LABEL: class Foo extends ExtModule {
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; CHECK-NEXT: val in = IO(Input(UInt(4.W)))
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; CHECK-NEXT: val out = IO(Output(UInt(4.W)))
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; CHECK-NEXT: }
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FIRRTL version 4.0.0
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circuit Foo:
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public module Foo:
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input in: UInt<4>
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output out: UInt<4>
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connect out, in
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