mirror of https://github.com/llvm/circt.git
43 lines
1.1 KiB
Plaintext
43 lines
1.1 KiB
Plaintext
; RUN: firtool %s | FileCheck %s
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; This is testing that CHIRRTL enable inference is working as intended. If the
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; no-op wires and nodes are not optimized away, then both ports should always
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; be enabled. If they are accidentally removed before the lower-chirrtl pass,
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; then they won't be enabled.
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FIRRTL version 4.0.0
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circuit test: %[[{
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"class": "sifive.enterprise.firrtl.MarkDUTAnnotation",
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"target":"~test|test"
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}]]
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public module test:
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input p: UInt<1>
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input addr1: UInt<4>
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input addr2: UInt<4>
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input addr3: UInt<4>
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input clock: Clock
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input data: UInt<8>
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output out0: UInt<8>
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output out1: UInt<8>
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; CHECK: testmem_16x8 testmem_ext (
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smem testmem : UInt<8>[16], undefined
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; CHECK: .R0_en (1'h1)
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node _T_0 = addr1
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when p:
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read mport testport0 = testmem[_T_0], clock
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connect out0, testport0
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; CHECK: .R1_en (1'h1),
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wire _T_1: UInt<4>
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connect _T_1, addr2
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when p:
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read mport testport1 = testmem[_T_1], clock
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connect out1, testport1
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node writeAddr = addr3
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when p:
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write mport testport2 = testmem[writeAddr], clock
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connect testport2, data
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