mirror of https://github.com/llvm/circt.git
67 lines
2.6 KiB
MLIR
67 lines
2.6 KiB
MLIR
// RUN: rm -rf %t
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// RUN: firtool %s --split-verilog -o=%t --blackbox-path=%S
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// RUN: FileCheck %s --check-prefix=VERILOG-TOP < %t/test_mod.sv
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// RUN: FileCheck %s --check-prefix=VERILOG-FOO < %t/magic/blackbox-inline.v
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// RUN: FileCheck %s --check-prefix=VERILOG-HDR < %t/magic/blackbox-inline.svh
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// RUN: FileCheck %s --check-prefix=VERILOG-GIB < %t/magic/blackbox-path.v
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// RUN: FileCheck %s --check-prefix=LIST-TOP < %t/filelist.f
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// RUN: FileCheck %s --check-prefix=LIST-BLACK-BOX < %t/magic.f
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// LIST-TOP: test_mod.sv
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// LIST-BLACK-BOX: magic{{[/\]}}blackbox-inline.v
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// LIST-BLACK-BOX-NEXT: magic{{[/\]}}blackbox-path.v
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firrtl.circuit "test_mod" attributes {annotations = [
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// Black box processing should honor only the last annotation.
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{class = "firrtl.transforms.BlackBoxTargetDirAnno", targetDir = "ignore_me_plz"},
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{class = "firrtl.transforms.BlackBoxTargetDirAnno", targetDir = "magic"},
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{class = "firrtl.transforms.BlackBoxResourceFileNameAnno", resourceFileName = "definitely_bad.f"},
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{class = "firrtl.transforms.BlackBoxResourceFileNameAnno", resourceFileName = "magic.f"}
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]} {
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// VERILOG-TOP-LABEL: module test_mod
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// VERILOG-TOP-NEXT: ExtInline foo
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// VERILOG-TOP-NEXT: ExtPath gib
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// VERILOG-TOP-NEXT: endmodule
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firrtl.module @test_mod() {
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firrtl.instance foo @ExtInline()
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firrtl.instance gib @ExtPath()
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}
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// VERILOG-FOO-LABEL: module ExtInline(); endmodule
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// This "//" is checking that file info is not printed.
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// VERILOG-FOO-NOT: //
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// VERILOG-FOO-NOT: module ExtInline(); endmodule
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// VERILOG-HDR-LABEL: `define SOME_MACRO
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// VERILOG-HDR-NOT: `define SOME_MACRO
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firrtl.extmodule @ExtInline() attributes {annotations = [
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// Inline file shall be emitted.
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{
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class = "firrtl.transforms.BlackBoxInlineAnno",
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name = "blackbox-inline.v",
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text = "module ExtInline(); endmodule\n"
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},
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// Duplicate inline annotations will not be emitted.
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{
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class = "firrtl.transforms.BlackBoxInlineAnno",
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name = "blackbox-inline.v",
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text = "module ExtInline(); endmodule\n"
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},
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// Verilog header `*.svh` shall be excluded from the file list.
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{
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class = "firrtl.transforms.BlackBoxInlineAnno",
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name = "blackbox-inline.svh",
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text = "`define SOME_MACRO\n"
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}
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], defname = "ExtInline"}
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// VERILOG-GIB-LABEL: module ExtPath(); endmodule
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// This "//" is checking that file info is not printed.
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// VERILOG-GIB-NOT: //
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// VERILOG-GIB-NOT: module ExtPath(); endmodule
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firrtl.extmodule @ExtPath() attributes {annotations = [{
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class = "firrtl.transforms.BlackBoxPathAnno",
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path = "blackbox-path.v"
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}], defname = "ExtPath"}
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}
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