mirror of https://github.com/llvm/circt.git
49 lines
1.6 KiB
Plaintext
49 lines
1.6 KiB
Plaintext
; This test checks the interaction between firtool's -o <file> option and
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; the assignment/resolution of output directories. Namely, does firtool actually
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; put verilog files in the right place.
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; RUN: firtool -split-verilog %s -o %t/design
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; RUN: FileCheck %s -input-file=%t/design/Foo.sv --check-prefix=FOO
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; RUN: FileCheck %s -input-file=%t/design/subdir/Bar.sv --check-prefix=BAR
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; RUN: FileCheck %s -input-file=%t/Baz.sv --check-prefix=BAZ
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; RUN: FileCheck %s -input-file=%t/design/XFoo.sv --check-prefix=XFOO
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; RUN: FileCheck %s -input-file=%t/design/subdir/XBar.sv --check-prefix=XBAR
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; RUN: FileCheck %s -input-file=%t/XBaz.sv --check-prefix=XBAZ
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; This test checks the interaction between firtool's -o <file> option and
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; the assignment/resolution of output directories.
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FIRRTL version 4.0.0
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circuit Foo: %[[
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{"class": "circt.OutputDirAnnotation", "target": "~Foo|Bar", "dirname": "subdir"},
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{"class": "circt.OutputDirAnnotation", "target": "~Foo|Baz", "dirname": ".."},
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{"class": "firrtl.transforms.DontTouchAnnotation", "target": "~Foo|XFoo>w"},
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{"class": "firrtl.transforms.DontTouchAnnotation", "target": "~Foo|XBar>w"},
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{"class": "firrtl.transforms.DontTouchAnnotation", "target": "~Foo|XBaz>w"}
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]]
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module XFoo:
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wire w : UInt<8>
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invalidate w
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module XBar:
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wire w : UInt<8>
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invalidate w
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module XBaz:
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wire w : UInt<8>
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invalidate w
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public module Foo:
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inst x of XFoo
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public module Bar:
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inst x of XBar
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public module Baz:
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inst x of XBaz
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; FOO: module Foo();
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; BAR: module Bar();
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; BAZ: module Baz();
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; XFOO: module XFoo();
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; XBAR: module XBar();
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; XBAZ: module XBaz();
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