mirror of https://github.com/llvm/circt.git
28 lines
803 B
Plaintext
28 lines
803 B
Plaintext
; RUN: firtool -parse-only %s | FileCheck %s
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FIRRTL version 4.0.0
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circuit OpenAgg : %[[
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{ "class": "circt.test",
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"target": "~OpenAgg|OpenAgg>out.a"
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},
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{ "class": "circt.test",
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"target": "~OpenAgg|OpenAgg>out.b"
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},
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{ "class": "circt.test",
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"target": "~OpenAgg|OpenAgg>out"
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}
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]]
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; CHECK-LABEL: module @OpenAgg
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; CHECK-SAME: (out %out: !firrtl.bundle<a: uint<1>, b: uint<1>> [{circt.fieldID = 1 : i32, class = "circt.test"}, {circt.fieldID = 2 : i32, class = "circt.test"}, {class = "circt.test"}]
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; CHECK-SAME: , out %out_p: !firrtl.probe<uint<1>>)
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public module OpenAgg:
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output out : {a : UInt<1>,
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p : Probe<UInt<1>>,
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b : UInt<1>}
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connect out.a, UInt<1>(1)
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connect out.b, UInt<1>(0)
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node n = out.a
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define out.p = probe(n)
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