mirror of https://github.com/llvm/circt.git
30 lines
1.1 KiB
Plaintext
30 lines
1.1 KiB
Plaintext
; RUN: firtool --parse-only %s | FileCheck %s
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FIRRTL version 4.0.0
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circuit Bar :
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public module Bar :
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input in: UInt<1>
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; Should create a "tap" node with the same type and a symbol when the type
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; is passive.
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wire a: UInt<1>
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; CHECK: %a = firrtl.wire interesting_name : !firrtl.uint<1>
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; Should use the non-tap wire in expressions.
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connect a, in
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; CHECK: firrtl.matchingconnect %a, %in
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; When the type is not passive, the tap should be a wire with the passive
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; type of the original wire.
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wire flip: {flip a: UInt<1>}
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; CHECK: %flip = firrtl.wire interesting_name : !firrtl.bundle<a flip: uint<1>>
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; Analog values should be tapped with a node.
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wire analog: Analog<1>
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; CHECK: %analog = firrtl.wire interesting_name : !firrtl.analog<1>
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; Should create attaches for analog typed elements between the tap wire and
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; the original wire.
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; https://github.com/llvm/circt/issues/2718
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wire w: {flip a: UInt<1>, b: Analog<1>}[1]
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; CHECK: %w = firrtl.wire interesting_name : !firrtl.vector<bundle<a flip: uint<1>, b: analog<1>>, 1>
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