mirror of https://github.com/llvm/circt.git
55 lines
1.5 KiB
Plaintext
55 lines
1.5 KiB
Plaintext
; RUN: firtool --split-input-file %s --ir-fir | FileCheck %s
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; Tests extracted from:
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; - test/scala/firrtlTests/WidthSpec.scala
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; Literal width checks
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FIRRTL version 3.0.0
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circuit Foo :
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; CHECK-LABEL: firrtl.module @Foo(
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; CHECK-SAME: out %si0: !firrtl.sint<3>
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; CHECK-SAME: out %si1: !firrtl.sint<3>
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; CHECK-SAME: out %si2: !firrtl.sint<2>
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; CHECK-SAME: out %si3: !firrtl.sint<1>
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; CHECK-SAME: out %si4: !firrtl.sint<1>
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; CHECK-SAME: out %si5: !firrtl.sint<2>
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; CHECK-SAME: out %si6: !firrtl.sint<3>
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; CHECK-SAME: out %si7: !firrtl.sint<3>
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; CHECK-SAME: out %si8: !firrtl.sint<4>
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; CHECK-SAME: out %ui0: !firrtl.uint<1>
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; CHECK-SAME: out %ui1: !firrtl.uint<1>
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; CHECK-SAME: out %ui2: !firrtl.uint<2>
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; CHECK-SAME: out %ui3: !firrtl.uint<2>
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; CHECK-SAME: out %ui4: !firrtl.uint<3>
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module Foo :
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output si0 : SInt
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output si1 : SInt
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output si2 : SInt
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output si3 : SInt
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output si4 : SInt
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output si5 : SInt
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output si6 : SInt
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output si7 : SInt
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output si8 : SInt
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output ui0 : UInt
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output ui1 : UInt
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output ui2 : UInt
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output ui3 : UInt
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output ui4 : UInt
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connect si0, SInt(-4)
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connect si1, SInt(-3)
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connect si2, SInt(-2)
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connect si3, SInt(-1)
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connect si4, SInt(0)
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connect si5, SInt(1)
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connect si6, SInt(2)
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connect si7, SInt(3)
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connect si8, SInt(4)
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connect ui0, UInt(0)
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connect ui1, UInt(1)
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connect ui2, UInt(2)
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connect ui3, UInt(3)
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connect ui4, UInt(4)
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