mirror of https://github.com/llvm/circt.git
128 lines
4.8 KiB
Plaintext
128 lines
4.8 KiB
Plaintext
; RUN: firtool --verilog -allow-adding-ports-on-public-modules %s | FileCheck %s
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; RUN: firtool --verilog -allow-adding-ports-on-public-modules -preserve-aggregate=1d-vec %s | FileCheck %s --check-prefix=AGGGREGATE
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; RUN: firtool --verilog -allow-adding-ports-on-public-modules -lower-annotations-no-ref-type-ports %s | FileCheck %s --check-prefix=NOREFS
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; RUN: firtool -allow-adding-ports-on-public-modules --parse-only %s | circt-opt --firrtl-probes-to-signals | firtool --verilog --format=mlir | FileCheck %s --check-prefix=PROBESTOSIGNALS
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FIRRTL version 4.0.0
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circuit Top : %[[
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{
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"class": "sifive.enterprise.firrtl.MarkDUTAnnotation",
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"target":"~Top|DUTModule"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~Top|Top>memTap"
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},
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{
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"class":"sifive.enterprise.grandcentral.MemTapAnnotation",
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"source":"~Top|DUTModule>rf",
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"sink":[
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"~Top|Top>memTap[0]",
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"~Top|Top>memTap[1]",
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"~Top|Top>memTap[2]",
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"~Top|Top>memTap[3]",
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"~Top|Top>memTap[4]",
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"~Top|Top>memTap[5]",
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"~Top|Top>memTap[6]",
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"~Top|Top>memTap[7]"
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]
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}
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]]
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module DUTModule :
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input clock : Clock
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input reset : Reset
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output io : { flip addr : UInt<3>, flip dataIn : UInt<8>, flip wen : UInt<1>, dataOut : UInt<8>}
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cmem rf : UInt<8> [8]
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infer mport read = rf[io.addr], clock
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connect io.dataOut, read
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when io.wen :
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infer mport write = rf[io.addr], clock
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connect write, io.dataIn
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public module Top :
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input clock : Clock
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input reset : UInt<1>
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output io : { flip addr : UInt<3>, flip dataIn : UInt<8>, flip wen : UInt<1>, dataOut : UInt<8>}
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inst dut of DUTModule
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connect dut.clock, clock
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connect dut.reset, reset
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wire memTap : UInt<8>[8]
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invalidate memTap
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connect io.dataOut, dut.io.dataOut
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connect dut.io.wen, io.wen
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connect dut.io.dataIn, io.dataIn
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connect dut.io.addr, io.addr
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; CHECK: module Top(
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; CHECK-NOT: module
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; CHECK: wire [7:0] memTap_0 = Top.dut.rf_ext.Memory[0];
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; CHECK-NEXT: wire [7:0] memTap_1 = Top.dut.rf_ext.Memory[1];
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; CHECK-NEXT: wire [7:0] memTap_2 = Top.dut.rf_ext.Memory[2];
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; CHECK-NEXT: wire [7:0] memTap_3 = Top.dut.rf_ext.Memory[3];
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; CHECK-NEXT: wire [7:0] memTap_4 = Top.dut.rf_ext.Memory[4];
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; CHECK-NEXT: wire [7:0] memTap_5 = Top.dut.rf_ext.Memory[5];
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; CHECK-NEXT: wire [7:0] memTap_6 = Top.dut.rf_ext.Memory[6];
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; CHECK-NEXT: wire [7:0] memTap_7 = Top.dut.rf_ext.Memory[7];
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; AGGGREGATE: wire [7:0][7:0] memTap =
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; AGGGREGATE-NEXT{LITERAL}: {{Top.dut.rf_ext.Memory[7]},
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; AGGGREGATE-NEXT: {Top.dut.rf_ext.Memory[6]},
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; AGGGREGATE-NEXT: {Top.dut.rf_ext.Memory[5]},
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; AGGGREGATE-NEXT: {Top.dut.rf_ext.Memory[4]},
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; AGGGREGATE-NEXT: {Top.dut.rf_ext.Memory[3]},
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; AGGGREGATE-NEXT: {Top.dut.rf_ext.Memory[2]},
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; AGGGREGATE-NEXT: {Top.dut.rf_ext.Memory[1]},
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; AGGGREGATE-NEXT: {Top.dut.rf_ext.Memory[0]}};
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; CHECK: endmodule
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; NOREFS: module DUTModule(
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; NOREFS-NOT: endmodule
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; NOREFS: rf_8x8 rf_ext (
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; NOREFS: .R1_data (memTap_7),
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; NOREFS: .R2_data (memTap_6),
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; NOREFS: .R3_data (memTap_5),
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; NOREFS: .R4_data (memTap_4),
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; NOREFS: .R5_data (memTap_3),
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; NOREFS: .R6_data (memTap_2),
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; NOREFS: .R7_data (memTap_1),
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; NOREFS: .R8_data (memTap_0)
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; NOREFS: )
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; NOREFS: endmodule
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; NOREFS: DUTModule dut (
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; NOREFS-NOT: endmodule
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; NOREFS: .memTap_0 (memTap_0),
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; NOREFS-NEXT: .memTap_1 (memTap_1),
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; NOREFS-NEXT: .memTap_2 (memTap_2),
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; NOREFS-NEXT: .memTap_3 (memTap_3),
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; NOREFS-NEXT: .memTap_4 (memTap_4),
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; NOREFS-NEXT: .memTap_5 (memTap_5),
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; NOREFS-NEXT: .memTap_6 (memTap_6),
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; NOREFS-NEXT: .memTap_7 (memTap_7)
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; NOREFS-NEXT: )
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; PROBESTOSIGNALS: module DUTModule(
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; PROBESTOSIGNALS-NOT: endmodule
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; PROBESTOSIGNALS: rf_8x8 rf_ext (
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; PROBESTOSIGNALS: .R1_data (memTap_0_7),
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; PROBESTOSIGNALS: .R2_data (memTap_0_6),
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; PROBESTOSIGNALS: .R3_data (memTap_0_5),
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; PROBESTOSIGNALS: .R4_data (memTap_0_4),
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; PROBESTOSIGNALS: .R5_data (memTap_0_3),
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; PROBESTOSIGNALS: .R6_data (memTap_0_2),
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; PROBESTOSIGNALS: .R7_data (memTap_0_1),
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; PROBESTOSIGNALS: .R8_data (memTap_0_0)
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; PROBESTOSIGNALS: )
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; PROBESTOSIGNALS: endmodule
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; PROBESTOSIGNALS: DUTModule dut (
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; PROBESTOSIGNALS-NOT: endmodule
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; PROBESTOSIGNALS: .memTap_0_0 (memTap_0),
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; PROBESTOSIGNALS-NEXT: .memTap_0_1 (memTap_1),
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; PROBESTOSIGNALS-NEXT: .memTap_0_2 (memTap_2),
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; PROBESTOSIGNALS-NEXT: .memTap_0_3 (memTap_3),
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; PROBESTOSIGNALS-NEXT: .memTap_0_4 (memTap_4),
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; PROBESTOSIGNALS-NEXT: .memTap_0_5 (memTap_5),
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; PROBESTOSIGNALS-NEXT: .memTap_0_6 (memTap_6),
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; PROBESTOSIGNALS-NEXT: .memTap_0_7 (memTap_7)
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; PROBESTOSIGNALS-NEXT: )
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