mirror of https://github.com/llvm/circt.git
1133 lines
25 KiB
Plaintext
1133 lines
25 KiB
Plaintext
; RUN: firtool -split-input-file -verilog %s | FileCheck %s
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; This test checks register removal behavior for situations where the register
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; is invalidated _through a primitive operation_. This is intended to tease out
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; gnarly bugs where, due to a combination of canonicalization, folding, and
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; constant propagation, CIRCT does not remove registers which the Scala FIRRTL
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; Compiler (SFC) does. The CHECK/CHECK-NOT statements in this test indicate the
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; SFC behavior.
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;
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; This test contains PASSING cases which are known to work. For failing cases
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; (which should be fixed and migrated into this file) see invalid-reg-fail.fir.
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;
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; The FIRRTL circuits in this file were generated using:
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; https://github.com/seldridge/firrtl-torture/blob/main/Invalid.scala
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FIRRTL version 4.0.0
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circuit add :
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public module add :
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input clock : Clock
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input reset : UInt<1>
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input in_0 : UInt<4>
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input in_1 : UInt<4>
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output out_0 : UInt<5>
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output out_1 : UInt<5>
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output out_2 : UInt<5>
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output out_3 : UInt<5>
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wire invalid : UInt<4>
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invalidate invalid
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reg r_0 : UInt<5>, clock
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reg r_1 : UInt<5>, clock
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reg r_2 : UInt<5>, clock
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reg r_3 : UInt<5>, clock
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node _T = add(in_1, in_0)
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node _T_1 = tail(_T, 1)
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connect r_0, _T_1
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connect out_0, r_0
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node _T_2 = add(in_1, invalid)
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node _T_3 = tail(_T_2, 1)
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connect r_1, _T_3
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connect out_1, r_1
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node _T_4 = add(invalid, in_0)
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node _T_5 = tail(_T_4, 1)
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connect r_2, _T_5
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connect out_2, r_2
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node _T_6 = add(invalid, invalid)
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node _T_7 = tail(_T_6, 1)
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connect r_3, _T_7
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connect out_3, r_3
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; CHECK-LABEL: module add
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; CHECK: r_0
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; CHECK: r_1
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; CHECK: r_2
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; CHECK-NOT: r_3
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; // -----
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FIRRTL version 4.0.0
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circuit and :
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public module and :
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input clock : Clock
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input reset : UInt<1>
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input in_0 : UInt<1>
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input in_1 : UInt<1>
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output out_0 : UInt<1>
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output out_1 : UInt<1>
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output out_2 : UInt<1>
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output out_3 : UInt<1>
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wire invalid : UInt<1>
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invalidate invalid
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reg r_0 : UInt<1>, clock
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reg r_1 : UInt<1>, clock
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reg r_2 : UInt<1>, clock
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reg r_3 : UInt<1>, clock
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node _T = and(in_1, in_0)
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connect r_0, _T
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connect out_0, r_0
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node _T_1 = and(in_1, invalid)
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connect r_1, _T_1
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connect out_1, r_1
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node _T_2 = and(invalid, in_0)
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connect r_2, _T_2
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connect out_2, r_2
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node _T_3 = and(invalid, invalid)
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connect r_3, _T_3
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connect out_3, r_3
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; CHECK-LABEL: module and
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; CHECK: r_0
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; CHECK-NOT: r_1
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; CHECK-NOT: r_2
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; CHECK-NOT: r_3
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; // -----
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FIRRTL version 4.0.0
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circuit asAsyncReset :
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public module asAsyncReset :
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input clock : Clock
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input reset : UInt<1>
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input in : UInt<1>
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output out_0 : AsyncReset
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output out_1 : AsyncReset
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wire invalid : UInt<1>
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invalidate invalid
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reg r_0 : AsyncReset, clock
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reg r_1 : AsyncReset, clock
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node _T = asAsyncReset(in)
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connect r_0, _T
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connect out_0, r_0
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node _T_1 = asAsyncReset(invalid)
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connect r_1, _T_1
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connect out_1, r_1
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; CHECK-LABEL: module asAsyncReset
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; CHECK: r_0
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; CHECK-NOT: r_1 <-- fixed; upstream to Scala FIRRTL impl?
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; // -----
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FIRRTL version 4.0.0
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circuit asClock :
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public module asClock :
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input clock : Clock
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input reset : UInt<1>
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input in : UInt<1>
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output out_0 : Clock
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output out_1 : Clock
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wire invalid : UInt<1>
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invalidate invalid
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reg r_0 : Clock, clock
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reg r_1 : Clock, clock
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node _T = asClock(in)
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connect r_0, _T
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connect out_0, r_0
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node _T_1 = asClock(invalid)
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connect r_1, _T_1
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connect out_1, r_1
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; CHECK-LABEL: module asClock
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; CHECK: r_0
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; CHECK-NOT: r_1 <-- fixed; upstream to Scala FIRRTL impl?
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; CHECK-NOT: r_2
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; CHECK-NOT: r_3
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; // -----
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FIRRTL version 4.0.0
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circuit cvt :
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public module cvt :
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input clock : Clock
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input reset : UInt<1>
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input in : UInt<4>
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output out_0 : SInt<5>
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output out_1 : SInt<5>
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wire invalid : UInt<4>
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invalidate invalid
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reg r_0 : SInt<5>, clock
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reg r_1 : SInt<5>, clock
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node _T = cvt(in)
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connect r_0, _T
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connect out_0, r_0
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node _T_1 = cvt(invalid)
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connect r_1, _T_1
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connect out_1, r_1
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; CHECK-LABEL: module cvt
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; CHECK: r_0
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; CHECK-NOT: r_1 <-- fixed; upstream to Scala FIRRTL impl?
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; CHECK-NOT: r_2
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; CHECK-NOT: r_3
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; // -----
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FIRRTL version 4.0.0
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circuit eq :
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public module eq :
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input clock : Clock
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input reset : UInt<1>
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input in_0 : UInt<4>
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input in_1 : UInt<4>
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output out_0 : UInt<1>
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output out_1 : UInt<1>
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output out_2 : UInt<1>
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output out_3 : UInt<1>
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wire invalid : UInt<4>
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invalidate invalid
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reg r_0 : UInt<1>, clock
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reg r_1 : UInt<1>, clock
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reg r_2 : UInt<1>, clock
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reg r_3 : UInt<1>, clock
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node _T = eq(in_1, in_0)
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connect r_0, _T
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connect out_0, r_0
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node _T_1 = eq(in_1, invalid)
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connect r_1, _T_1
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connect out_1, r_1
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node _T_2 = eq(invalid, in_0)
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connect r_2, _T_2
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connect out_2, r_2
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node _T_3 = eq(invalid, invalid)
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connect r_3, _T_3
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connect out_3, r_3
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; CHECK-LABEL: module eq
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; CHECK: r_0
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; CHECK: r_1
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; CHECK: r_2
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; CHECK-NOT: r_3
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; // -----
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FIRRTL version 4.0.0
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circuit neg :
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public module neg :
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input clock : Clock
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input reset : UInt<1>
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input in : UInt<4>
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output out_0 : UInt<5>
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output out_1 : UInt<5>
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wire invalid : UInt<4>
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invalidate invalid
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reg r_0 : UInt<5>, clock
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reg r_1 : UInt<5>, clock
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node _T = sub(UInt<1>(0h0), in)
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node _T_1 = tail(_T, 1)
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connect r_0, _T_1
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connect out_0, r_0
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node _T_2 = sub(UInt<1>(0h0), invalid)
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node _T_3 = tail(_T_2, 1)
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connect r_1, _T_3
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connect out_1, r_1
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; CHECK-LABEL: module neg
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; CHECK: r_0
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; CHECK-NOT: r_1
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; CHECK-NOT: r_2
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; CHECK-NOT: r_3
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; // -----
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FIRRTL version 4.0.0
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circuit neq :
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public module neq :
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input clock : Clock
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input reset : UInt<1>
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input in_0 : UInt<4>
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input in_1 : UInt<4>
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output out_0 : UInt<1>
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output out_1 : UInt<1>
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output out_2 : UInt<1>
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output out_3 : UInt<1>
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wire invalid : UInt<4>
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invalidate invalid
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reg r_0 : UInt<1>, clock
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reg r_1 : UInt<1>, clock
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reg r_2 : UInt<1>, clock
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reg r_3 : UInt<1>, clock
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node _T = neq(in_1, in_0)
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connect r_0, _T
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connect out_0, r_0
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node _T_1 = neq(in_1, invalid)
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connect r_1, _T_1
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connect out_1, r_1
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node _T_2 = neq(invalid, in_0)
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connect r_2, _T_2
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connect out_2, r_2
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node _T_3 = neq(invalid, invalid)
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connect r_3, _T_3
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connect out_3, r_3
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; CHECK-LABEL: module neq
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; CHECK: r_0
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; CHECK: r_1
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; CHECK: r_2
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; CHECK-NOT: r_3
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; // -----
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FIRRTL version 4.0.0
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circuit or :
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public module or :
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input clock : Clock
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input reset : UInt<1>
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input in_0 : UInt<1>
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input in_1 : UInt<1>
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output out_0 : UInt<1>
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output out_1 : UInt<1>
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output out_2 : UInt<1>
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output out_3 : UInt<1>
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wire invalid : UInt<1>
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invalidate invalid
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reg r_0 : UInt<1>, clock
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reg r_1 : UInt<1>, clock
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reg r_2 : UInt<1>, clock
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reg r_3 : UInt<1>, clock
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node _T = or(in_1, in_0)
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connect r_0, _T
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connect out_0, r_0
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node _T_1 = or(in_1, invalid)
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connect r_1, _T_1
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connect out_1, r_1
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node _T_2 = or(invalid, in_0)
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connect r_2, _T_2
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connect out_2, r_2
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node _T_3 = or(invalid, invalid)
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connect r_3, _T_3
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connect out_3, r_3
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; CHECK-LABEL: module or
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; CHECK: r_0
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; CHECK: r_1
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; CHECK: r_2
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; CHECK-NOT: r_3
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; // -----
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FIRRTL version 4.0.0
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circuit pad :
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public module pad :
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input clock : Clock
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input reset : UInt<1>
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input in : UInt<1>
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output out_0 : UInt<2>
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output out_1 : UInt<2>
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wire invalid : UInt<1>
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invalidate invalid
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reg r_0 : UInt<2>, clock
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reg r_1 : UInt<2>, clock
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node _T = pad(in, 2)
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connect r_0, _T
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connect out_0, r_0
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node _T_1 = pad(invalid, 2)
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connect r_1, _T_1
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connect out_1, r_1
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; CHECK-LABEL: module pad
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; CHECK: r_0
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; CHECK-NOT: r_1
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; CHECK-NOT: r_2
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; CHECK-NOT: r_3
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; // -----
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FIRRTL version 4.0.0
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circuit xor :
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public module xor :
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input clock : Clock
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input reset : UInt<1>
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input in_0 : UInt<1>
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input in_1 : UInt<1>
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output out_0 : UInt<1>
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output out_1 : UInt<1>
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output out_2 : UInt<1>
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output out_3 : UInt<1>
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wire invalid : UInt<1>
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invalidate invalid
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reg r_0 : UInt<1>, clock
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reg r_1 : UInt<1>, clock
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reg r_2 : UInt<1>, clock
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reg r_3 : UInt<1>, clock
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node _T = xor(in_1, in_0)
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connect r_0, _T
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connect out_0, r_0
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node _T_1 = xor(in_1, invalid)
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connect r_1, _T_1
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connect out_1, r_1
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node _T_2 = xor(invalid, in_0)
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connect r_2, _T_2
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connect out_2, r_2
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node _T_3 = xor(invalid, invalid)
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connect r_3, _T_3
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connect out_3, r_3
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; CHECK-LABEL: module xor
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; CHECK: r_0
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; CHECK: r_1
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; CHECK: r_2
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; CHECK-NOT: r_3
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; // -----
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FIRRTL version 4.0.0
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circuit andr :
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public module andr :
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input clock : Clock
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input reset : UInt<1>
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input in : UInt<4>
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output out_0 : UInt<1>
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output out_1 : UInt<1>
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wire invalid : UInt<4>
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invalidate invalid
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reg r_0 : UInt<1>, clock
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reg r_1 : UInt<1>, clock
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node _T = andr(in)
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connect r_0, _T
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connect out_0, r_0
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node _T_1 = andr(invalid)
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connect r_1, _T_1
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connect out_1, r_1
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; CHECK-LABEL: module andr
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; CHECK: r_0
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; CHECK-NOT: r_1
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; CHECK-NOT: r_2
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; CHECK-NOT: r_3
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; // -----
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FIRRTL version 4.0.0
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circuit asSInt :
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public module asSInt :
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input clock : Clock
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input reset : UInt<1>
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input in : UInt<2>
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output out_0 : SInt<2>
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output out_1 : SInt<2>
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wire invalid : UInt<2>
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invalidate invalid
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reg r_0 : SInt<2>, clock
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reg r_1 : SInt<2>, clock
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node _T = asSInt(in)
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connect r_0, _T
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connect out_0, r_0
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node _T_1 = asSInt(invalid)
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connect r_1, _T_1
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connect out_1, r_1
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; CHECK-LABEL: module asSInt
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; CHECK: r_0
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; CHECK-NOT: r_1
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; CHECK-NOT: r_2
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; CHECK-NOT: r_3
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; // -----
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FIRRTL version 4.0.0
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circuit asUInt :
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public module asUInt :
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input clock : Clock
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input reset : UInt<1>
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input in : SInt<2>
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output out_0 : UInt<2>
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output out_1 : UInt<2>
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wire invalid : SInt<2>
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invalidate invalid
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reg r_0 : UInt<2>, clock
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reg r_1 : UInt<2>, clock
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node _T = asUInt(in)
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connect r_0, _T
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connect out_0, r_0
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node _T_1 = asUInt(invalid)
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connect r_1, _T_1
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connect out_1, r_1
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; CHECK-LABEL: module asUInt
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; CHECK: r_0
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; CHECK-NOT: r_1
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; CHECK-NOT: r_2
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; CHECK-NOT: r_3
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; // -----
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FIRRTL version 4.0.0
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circuit bits :
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public module bits :
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input clock : Clock
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input reset : UInt<1>
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input in : UInt<4>
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output out_0 : UInt<2>
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output out_1 : UInt<2>
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wire invalid : UInt<4>
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invalidate invalid
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reg r_0 : UInt<2>, clock
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reg r_1 : UInt<2>, clock
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node _T = bits(in, 3, 2)
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connect r_0, _T
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connect out_0, r_0
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node _T_1 = bits(invalid, 3, 2)
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connect r_1, _T_1
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connect out_1, r_1
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; CHECK-LABEL: module bits
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; CHECK: r_0
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; CHECK-NOT: r_1
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; CHECK-NOT: r_2
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; CHECK-NOT: r_3
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; // -----
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FIRRTL version 4.0.0
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circuit cat :
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public module cat :
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input clock : Clock
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input reset : UInt<1>
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input in_0 : UInt<2>
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input in_1 : UInt<2>
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output out_0 : UInt<4>
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output out_1 : UInt<4>
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output out_2 : UInt<4>
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output out_3 : UInt<4>
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wire invalid : UInt<2>
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invalidate invalid
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reg r_0 : UInt<4>, clock
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reg r_1 : UInt<4>, clock
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reg r_2 : UInt<4>, clock
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reg r_3 : UInt<4>, clock
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node _T = cat(in_1, in_0)
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connect r_0, _T
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connect out_0, r_0
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node _T_1 = cat(in_1, invalid)
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connect r_1, _T_1
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connect out_1, r_1
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node _T_2 = cat(invalid, in_0)
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connect r_2, _T_2
|
|
connect out_2, r_2
|
|
node _T_3 = cat(invalid, invalid)
|
|
connect r_3, _T_3
|
|
connect out_3, r_3
|
|
|
|
; CHECK-LABEL: module cat
|
|
; CHECK: r_0
|
|
; CHECK: r_1
|
|
; CHECK: r_2
|
|
; CHECK-NOT: r_3
|
|
|
|
; // -----
|
|
|
|
FIRRTL version 4.0.0
|
|
circuit dshl :
|
|
public module dshl :
|
|
input clock : Clock
|
|
input reset : UInt<1>
|
|
input in_0 : UInt<2>
|
|
input in_1 : UInt<2>
|
|
output out_0 : UInt<5>
|
|
output out_1 : UInt<5>
|
|
output out_2 : UInt<5>
|
|
output out_3 : UInt<5>
|
|
|
|
wire invalid : UInt<2>
|
|
invalidate invalid
|
|
reg r_0 : UInt<5>, clock
|
|
reg r_1 : UInt<5>, clock
|
|
reg r_2 : UInt<5>, clock
|
|
reg r_3 : UInt<5>, clock
|
|
node _T = dshl(in_1, in_0)
|
|
connect r_0, _T
|
|
connect out_0, r_0
|
|
node _T_1 = dshl(in_1, invalid)
|
|
connect r_1, _T_1
|
|
connect out_1, r_1
|
|
node _T_2 = dshl(invalid, in_0)
|
|
connect r_2, _T_2
|
|
connect out_2, r_2
|
|
node _T_3 = dshl(invalid, invalid)
|
|
connect r_3, _T_3
|
|
connect out_3, r_3
|
|
|
|
; CHECK-LABEL: module dshl
|
|
; CHECK: r_0
|
|
; CHECK: r_1
|
|
; CHECK: r_2
|
|
; CHECK-NOT: r_3
|
|
|
|
; // -----
|
|
|
|
FIRRTL version 4.0.0
|
|
circuit dshr :
|
|
public module dshr :
|
|
input clock : Clock
|
|
input reset : UInt<1>
|
|
input in_0 : UInt<2>
|
|
input in_1 : UInt<2>
|
|
output out_0 : UInt<2>
|
|
output out_1 : UInt<2>
|
|
output out_2 : UInt<2>
|
|
output out_3 : UInt<2>
|
|
|
|
wire invalid : UInt<2>
|
|
invalidate invalid
|
|
reg r_0 : UInt<2>, clock
|
|
reg r_1 : UInt<2>, clock
|
|
reg r_2 : UInt<2>, clock
|
|
reg r_3 : UInt<2>, clock
|
|
node _T = dshr(in_1, in_0)
|
|
connect r_0, _T
|
|
connect out_0, r_0
|
|
node _T_1 = dshr(in_1, invalid)
|
|
connect r_1, _T_1
|
|
connect out_1, r_1
|
|
node _T_2 = dshr(invalid, in_0)
|
|
connect r_2, _T_2
|
|
connect out_2, r_2
|
|
node _T_3 = dshr(invalid, invalid)
|
|
connect r_3, _T_3
|
|
connect out_3, r_3
|
|
|
|
; CHECK-LABEL: module dshr
|
|
; CHECK: r_0
|
|
; CHECK: r_1
|
|
; CHECK: r_2
|
|
; CHECK-NOT: r_3
|
|
|
|
; // -----
|
|
|
|
FIRRTL version 4.0.0
|
|
circuit head :
|
|
public module head :
|
|
input clock : Clock
|
|
input reset : UInt<1>
|
|
input in : UInt<4>
|
|
output out_0 : UInt<2>
|
|
output out_1 : UInt<2>
|
|
|
|
wire invalid : UInt<4>
|
|
invalidate invalid
|
|
reg r_0 : UInt<2>, clock
|
|
reg r_1 : UInt<2>, clock
|
|
node _T = head(in, 2)
|
|
connect r_0, _T
|
|
connect out_0, r_0
|
|
node _T_1 = head(invalid, 2)
|
|
connect r_1, _T_1
|
|
connect out_1, r_1
|
|
|
|
; CHECK-LABEL: module head
|
|
; CHECK: r_0
|
|
; CHECK-NOT: r_1
|
|
; CHECK-NOT: r_2
|
|
; CHECK-NOT: r_3
|
|
|
|
; // -----
|
|
|
|
FIRRTL version 4.0.0
|
|
circuit lt :
|
|
public module lt :
|
|
input clock : Clock
|
|
input reset : UInt<1>
|
|
input in_0 : UInt<4>
|
|
input in_1 : UInt<4>
|
|
output out_0 : UInt<1>
|
|
output out_1 : UInt<1>
|
|
output out_2 : UInt<1>
|
|
output out_3 : UInt<1>
|
|
|
|
wire invalid : UInt<4>
|
|
invalidate invalid
|
|
reg r_0 : UInt<1>, clock
|
|
reg r_1 : UInt<1>, clock
|
|
reg r_2 : UInt<1>, clock
|
|
reg r_3 : UInt<1>, clock
|
|
node _T = lt(in_1, in_0)
|
|
connect r_0, _T
|
|
connect out_0, r_0
|
|
node _T_1 = lt(in_1, invalid)
|
|
connect r_1, _T_1
|
|
connect out_1, r_1
|
|
node _T_2 = lt(invalid, in_0)
|
|
connect r_2, _T_2
|
|
connect out_2, r_2
|
|
node _T_3 = lt(invalid, invalid)
|
|
connect r_3, _T_3
|
|
connect out_3, r_3
|
|
|
|
; CHECK-LABEL: module lt
|
|
; CHECK: r_0
|
|
; CHECK-NOT: r_1
|
|
; CHECK: r_2
|
|
; CHECK-NOT: r_3
|
|
|
|
; // -----
|
|
|
|
FIRRTL version 4.0.0
|
|
circuit gt :
|
|
public module gt :
|
|
input clock : Clock
|
|
input reset : UInt<1>
|
|
input in_0 : UInt<4>
|
|
input in_1 : UInt<4>
|
|
output out_0 : UInt<1>
|
|
output out_1 : UInt<1>
|
|
output out_2 : UInt<1>
|
|
output out_3 : UInt<1>
|
|
|
|
wire invalid : UInt<4>
|
|
invalidate invalid
|
|
reg r_0 : UInt<1>, clock
|
|
reg r_1 : UInt<1>, clock
|
|
reg r_2 : UInt<1>, clock
|
|
reg r_3 : UInt<1>, clock
|
|
node _T = gt(in_1, in_0)
|
|
connect r_0, _T
|
|
connect out_0, r_0
|
|
node _T_1 = gt(in_1, invalid)
|
|
connect r_1, _T_1
|
|
connect out_1, r_1
|
|
node _T_2 = gt(invalid, in_0)
|
|
connect r_2, _T_2
|
|
connect out_2, r_2
|
|
node _T_3 = gt(invalid, invalid)
|
|
connect r_3, _T_3
|
|
connect out_3, r_3
|
|
|
|
; CHECK-LABEL: module gt
|
|
; CHECK: r_0
|
|
; CHECK: r_1
|
|
; CHECK-NOT: r_2
|
|
; CHECK-NOT: r_3
|
|
|
|
; // -----
|
|
|
|
FIRRTL version 4.0.0
|
|
circuit leq :
|
|
public module leq :
|
|
input clock : Clock
|
|
input reset : UInt<1>
|
|
input in_0 : UInt<4>
|
|
input in_1 : UInt<4>
|
|
output out_0 : UInt<1>
|
|
output out_1 : UInt<1>
|
|
output out_2 : UInt<1>
|
|
output out_3 : UInt<1>
|
|
|
|
wire invalid : UInt<4>
|
|
invalidate invalid
|
|
reg r_0 : UInt<1>, clock
|
|
reg r_1 : UInt<1>, clock
|
|
reg r_2 : UInt<1>, clock
|
|
reg r_3 : UInt<1>, clock
|
|
node _T = leq(in_1, in_0)
|
|
connect r_0, _T
|
|
connect out_0, r_0
|
|
node _T_1 = leq(in_1, invalid)
|
|
connect r_1, _T_1
|
|
connect out_1, r_1
|
|
node _T_2 = leq(invalid, in_0)
|
|
connect r_2, _T_2
|
|
connect out_2, r_2
|
|
node _T_3 = leq(invalid, invalid)
|
|
connect r_3, _T_3
|
|
connect out_3, r_3
|
|
|
|
; CHECK-LABEL: module leq
|
|
; CHECK: r_0
|
|
; CHECK: r_1
|
|
; CHECK-NOT: r_2
|
|
; CHECK-NOT: r_3
|
|
|
|
; // -----
|
|
|
|
FIRRTL version 4.0.0
|
|
circuit geq :
|
|
public module geq :
|
|
input clock : Clock
|
|
input reset : UInt<1>
|
|
input in_0 : UInt<4>
|
|
input in_1 : UInt<4>
|
|
output out_0 : UInt<1>
|
|
output out_1 : UInt<1>
|
|
output out_2 : UInt<1>
|
|
output out_3 : UInt<1>
|
|
|
|
wire invalid : UInt<4>
|
|
invalidate invalid
|
|
reg r_0 : UInt<1>, clock
|
|
reg r_1 : UInt<1>, clock
|
|
reg r_2 : UInt<1>, clock
|
|
reg r_3 : UInt<1>, clock
|
|
node _T = geq(in_1, in_0)
|
|
connect r_0, _T
|
|
connect out_0, r_0
|
|
node _T_1 = geq(in_1, invalid)
|
|
connect r_1, _T_1
|
|
connect out_1, r_1
|
|
node _T_2 = geq(invalid, in_0)
|
|
connect r_2, _T_2
|
|
connect out_2, r_2
|
|
node _T_3 = geq(invalid, invalid)
|
|
connect r_3, _T_3
|
|
connect out_3, r_3
|
|
|
|
; CHECK-LABEL: module geq
|
|
; CHECK: r_0
|
|
; CHECK-NOT: r_1
|
|
; CHECK: r_2
|
|
; CHECK-NOT: r_3
|
|
|
|
; // -----
|
|
|
|
FIRRTL version 4.0.0
|
|
circuit mul :
|
|
public module mul :
|
|
input clock : Clock
|
|
input reset : UInt<1>
|
|
input in_0 : UInt<4>
|
|
input in_1 : UInt<4>
|
|
output out_0 : UInt<8>
|
|
output out_1 : UInt<8>
|
|
output out_2 : UInt<8>
|
|
output out_3 : UInt<8>
|
|
|
|
wire invalid : UInt<4>
|
|
invalidate invalid
|
|
reg r_0 : UInt<8>, clock
|
|
reg r_1 : UInt<8>, clock
|
|
reg r_2 : UInt<8>, clock
|
|
reg r_3 : UInt<8>, clock
|
|
node _T = mul(in_1, in_0)
|
|
connect r_0, _T
|
|
connect out_0, r_0
|
|
node _T_1 = mul(in_1, invalid)
|
|
connect r_1, _T_1
|
|
connect out_1, r_1
|
|
node _T_2 = mul(invalid, in_0)
|
|
connect r_2, _T_2
|
|
connect out_2, r_2
|
|
node _T_3 = mul(invalid, invalid)
|
|
connect r_3, _T_3
|
|
connect out_3, r_3
|
|
|
|
; CHECK-LABEL: module mul
|
|
; CHECK: r_0
|
|
; CHECK-NOT: r_1 <-- fixed; upstream to Scala FIRRTL impl?
|
|
; CHECK-NOT: r_2 <-- fixed; upstream to Scala FIRRTL impl?
|
|
; CHECK-NOT: r_3 <-- fixed; upstream to Scala FIRRTL impl?
|
|
|
|
; // -----
|
|
|
|
FIRRTL version 4.0.0
|
|
circuit not :
|
|
public module not :
|
|
input clock : Clock
|
|
input reset : UInt<1>
|
|
input in : UInt<4>
|
|
output out_0 : UInt<4>
|
|
output out_1 : UInt<4>
|
|
|
|
wire invalid : UInt<4>
|
|
invalidate invalid
|
|
reg r_0 : UInt<4>, clock
|
|
reg r_1 : UInt<4>, clock
|
|
node _T = not(in)
|
|
connect r_0, _T
|
|
connect out_0, r_0
|
|
node _T_1 = not(invalid)
|
|
connect r_1, _T_1
|
|
connect out_1, r_1
|
|
|
|
; CHECK-LABEL: module not
|
|
; CHECK: r_0
|
|
; CHECK-NOT: r_1
|
|
; CHECK-NOT: r_2
|
|
; CHECK-NOT: r_3
|
|
|
|
; // -----
|
|
|
|
FIRRTL version 4.0.0
|
|
circuit orr :
|
|
public module orr :
|
|
input clock : Clock
|
|
input reset : UInt<1>
|
|
input in : UInt<4>
|
|
output out_0 : UInt<1>
|
|
output out_1 : UInt<1>
|
|
|
|
wire invalid : UInt<4>
|
|
invalidate invalid
|
|
reg r_0 : UInt<1>, clock
|
|
reg r_1 : UInt<1>, clock
|
|
node _T = orr(in)
|
|
connect r_0, _T
|
|
connect out_0, r_0
|
|
node _T_1 = orr(invalid)
|
|
connect r_1, _T_1
|
|
connect out_1, r_1
|
|
|
|
; CHECK-LABEL: module orr
|
|
; CHECK: r_0
|
|
; CHECK-NOT: r_1
|
|
; CHECK-NOT: r_2
|
|
; CHECK-NOT: r_3
|
|
|
|
; // -----
|
|
|
|
FIRRTL version 4.0.0
|
|
circuit shl :
|
|
public module shl :
|
|
input clock : Clock
|
|
input reset : UInt<1>
|
|
input in : UInt<2>
|
|
output out_0 : UInt<4>
|
|
output out_1 : UInt<4>
|
|
|
|
wire invalid : UInt<2>
|
|
invalidate invalid
|
|
reg r_0 : UInt<4>, clock
|
|
reg r_1 : UInt<4>, clock
|
|
node _T = shl(in, 2)
|
|
connect r_0, _T
|
|
connect out_0, r_0
|
|
node _T_1 = shl(invalid, 2)
|
|
connect r_1, _T_1
|
|
connect out_1, r_1
|
|
|
|
; CHECK-LABEL: module shl
|
|
; CHECK: r_0
|
|
; CHECK-NOT: r_1
|
|
; CHECK-NOT: r_2
|
|
; CHECK-NOT: r_3
|
|
|
|
; // -----
|
|
|
|
FIRRTL version 4.0.0
|
|
circuit shr :
|
|
public module shr :
|
|
input clock : Clock
|
|
input reset : UInt<1>
|
|
input in : UInt<4>
|
|
output out_0 : UInt<2>
|
|
output out_1 : UInt<2>
|
|
|
|
wire invalid : UInt<4>
|
|
invalidate invalid
|
|
reg r_0 : UInt<2>, clock
|
|
reg r_1 : UInt<2>, clock
|
|
node _T = shr(in, 2)
|
|
connect r_0, _T
|
|
connect out_0, r_0
|
|
node _T_1 = shr(invalid, 2)
|
|
connect r_1, _T_1
|
|
connect out_1, r_1
|
|
|
|
; CHECK-LABEL: module shr
|
|
; CHECK: r_0
|
|
; CHECK-NOT: r_1
|
|
; CHECK-NOT: r_2
|
|
; CHECK-NOT: r_3
|
|
|
|
; // -----
|
|
|
|
FIRRTL version 4.0.0
|
|
circuit sub :
|
|
public module sub :
|
|
input clock : Clock
|
|
input reset : UInt<1>
|
|
input in_0 : UInt<4>
|
|
input in_1 : UInt<4>
|
|
output out_0 : UInt<5>
|
|
output out_1 : UInt<5>
|
|
output out_2 : UInt<5>
|
|
output out_3 : UInt<5>
|
|
|
|
wire invalid : UInt<4>
|
|
invalidate invalid
|
|
reg r_0 : UInt<5>, clock
|
|
reg r_1 : UInt<5>, clock
|
|
reg r_2 : UInt<5>, clock
|
|
reg r_3 : UInt<5>, clock
|
|
node _T = sub(in_1, in_0)
|
|
node _T_1 = tail(_T, 1)
|
|
connect r_0, _T_1
|
|
connect out_0, r_0
|
|
node _T_2 = sub(in_1, invalid)
|
|
node _T_3 = tail(_T_2, 1)
|
|
connect r_1, _T_3
|
|
connect out_1, r_1
|
|
node _T_4 = sub(invalid, in_0)
|
|
node _T_5 = tail(_T_4, 1)
|
|
connect r_2, _T_5
|
|
connect out_2, r_2
|
|
node _T_6 = sub(invalid, invalid)
|
|
node _T_7 = tail(_T_6, 1)
|
|
connect r_3, _T_7
|
|
connect out_3, r_3
|
|
|
|
; CHECK-LABEL: module sub
|
|
; CHECK: r_0
|
|
; CHECK: r_1
|
|
; CHECK: r_2
|
|
; CHECK-NOT: r_3
|
|
|
|
; // -----
|
|
|
|
FIRRTL version 4.0.0
|
|
circuit tail :
|
|
public module tail :
|
|
input clock : Clock
|
|
input reset : UInt<1>
|
|
input in : UInt<4>
|
|
output out_0 : UInt<2>
|
|
output out_1 : UInt<2>
|
|
|
|
wire invalid : UInt<4>
|
|
invalidate invalid
|
|
reg r_0 : UInt<2>, clock
|
|
reg r_1 : UInt<2>, clock
|
|
node _T = tail(in, 2)
|
|
connect r_0, _T
|
|
connect out_0, r_0
|
|
node _T_1 = tail(invalid, 2)
|
|
connect r_1, _T_1
|
|
connect out_1, r_1
|
|
|
|
; CHECK-LABEL: module tail
|
|
; CHECK: r_0
|
|
; CHECK-NOT: r_1
|
|
; CHECK-NOT: r_2
|
|
; CHECK-NOT: r_3
|
|
|
|
; // -----
|
|
|
|
FIRRTL version 4.0.0
|
|
circuit div :
|
|
public module div :
|
|
input clock : Clock
|
|
input reset : UInt<1>
|
|
input in_0 : UInt<4>
|
|
input in_1 : UInt<4>
|
|
output out_0 : UInt<4>
|
|
output out_1 : UInt<4>
|
|
output out_2 : UInt<4>
|
|
output out_3 : UInt<4>
|
|
|
|
wire invalid : UInt<4>
|
|
invalidate invalid
|
|
reg r_0 : UInt<4>, clock
|
|
reg r_1 : UInt<4>, clock
|
|
reg r_2 : UInt<4>, clock
|
|
reg r_3 : UInt<4>, clock
|
|
node _T = div(in_1, in_0)
|
|
connect r_0, _T
|
|
connect out_0, r_0
|
|
node _T_1 = div(in_1, invalid)
|
|
connect r_1, _T_1
|
|
connect out_1, r_1
|
|
node _T_2 = div(invalid, in_0)
|
|
connect r_2, _T_2
|
|
connect out_2, r_2
|
|
node _T_3 = div(invalid, invalid)
|
|
connect r_3, _T_3
|
|
connect out_3, r_3
|
|
|
|
; CHECK-LABEL: module div
|
|
; CHECK: r_0
|
|
; CHECK: r_1
|
|
; CHECK-NOT: r_2 <-- fixed; upstream to Scala FIRRTL impl?
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; CHECK-NOT: r_3
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; // -----
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FIRRTL version 4.0.0
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circuit rem :
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public module rem :
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input clock : Clock
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input reset : UInt<1>
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input in_0 : UInt<4>
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input in_1 : UInt<4>
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output out_0 : UInt<4>
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output out_1 : UInt<4>
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output out_2 : UInt<4>
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output out_3 : UInt<4>
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wire invalid : UInt<4>
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invalidate invalid
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reg r_0 : UInt<4>, clock
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reg r_1 : UInt<4>, clock
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reg r_2 : UInt<4>, clock
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reg r_3 : UInt<4>, clock
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node _T = rem(in_1, in_0)
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connect r_0, _T
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connect out_0, r_0
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node _T_1 = rem(in_1, invalid)
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connect r_1, _T_1
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connect out_1, r_1
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node _T_2 = rem(invalid, in_0)
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connect r_2, _T_2
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connect out_2, r_2
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node _T_3 = rem(invalid, invalid)
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connect r_3, _T_3
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connect out_3, r_3
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; CHECK-LABEL: module rem
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; CHECK: r_0
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; CHECK: r_1
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; CHECK-NOT: r_2 <-- fixed; upstream to Scala FIRRTL impl?
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|
; CHECK-NOT: r_3
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|
|
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; // -----
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FIRRTL version 4.0.0
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circuit xorr :
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public module xorr :
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input clock : Clock
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input reset : UInt<1>
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input in : UInt<4>
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output out_0 : UInt<1>
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output out_1 : UInt<1>
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|
|
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wire invalid : UInt<4>
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invalidate invalid
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reg r_0 : UInt<1>, clock
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reg r_1 : UInt<1>, clock
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node _T = xorr(in)
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connect r_0, _T
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connect out_0, r_0
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node _T_1 = xorr(invalid)
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connect r_1, _T_1
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connect out_1, r_1
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; CHECK-LABEL: module xorr
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; CHECK: r_0
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; CHECK-NOT: r_1
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; CHECK-NOT: r_2
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; CHECK-NOT: r_3
|