mirror of https://github.com/llvm/circt.git
73 lines
2.1 KiB
Plaintext
73 lines
2.1 KiB
Plaintext
; RUN: firtool -split-input-file -verilog %s | FileCheck %s
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; This test checks end-to-end compliance with the Scala FIRRTL Compiler (SFC)
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; context-sensitive interpretation of invalid.
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; CHECK-LABEL: module InvalidInterpretations
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FIRRTL version 4.0.0
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circuit InvalidInterpretations:
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public module InvalidInterpretations:
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input clock: Clock
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input reset: UInt<1>
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input cond: UInt<1>
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input a: UInt<8>
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output out_when: UInt<8>
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output out_reg: UInt<8>
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output out_mux: UInt<8>
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output out_add: UInt<9>
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wire _inv: UInt<8>
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invalidate _inv
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regreset r: UInt<8>, clock, reset, _inv
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connect r, a
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connect out_reg, r
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; Interpretation 1: Invalid is undefined if used as the initialization value
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; of a register in a module-scoped analysis that looks through connects.
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; CHECK: always @(posedge clock)
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; CHECK-NOT: if (reset)
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invalidate out_when
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when cond:
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connect out_when, a
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; Interpretation 2: Invalid is undefined when used as a default value.
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; CHECK: assign out_when = a;
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connect out_mux, mux(cond, a, _inv)
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connect out_add, add(a, _inv)
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; Interpretation 4: Invalid is zero otherwise.
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; CHECK: assign out_mux = cond ? a : 8'h0;
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; CHECK-NEXT: assign out_add = {1'h0, a};
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; // -----
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; This is checking that an invalid value in another module is not propagated,
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; but is interpreted as "zero". The end result of this is that the main module
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; should have a register that will be reset to a non-zero value, but is
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; constantly driven to zero by default.
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;
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; See: https://github.com/llvm/circt/issues/2782
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; CHECK-LABEL: module InvalidInOtherModule
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FIRRTL version 4.0.0
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circuit InvalidInOtherModule :
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public module InvalidInOtherModule :
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input clock: Clock
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input reset: UInt<1>
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output b: SInt<8>
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inst other of OtherModule
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; CHECK: always @(posedge clock)
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; CHECK-NEXT: if (reset)
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; CHECK-NEXT: r <= 8'h4;
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; CHECK-NEXT: else
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; CHECK-NEXT: r <= 8'h0;
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regreset r : SInt<8>, clock, reset, SInt<8>(4)
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connect r, other.b
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connect b, r
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module OtherModule :
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output b: SInt<8>
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invalidate b
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