mirror of https://github.com/llvm/circt.git
211 lines
9.6 KiB
Plaintext
211 lines
9.6 KiB
Plaintext
; RUN: firtool %s -disable-all-randomization -disable-opt -annotation-file %s.sitestblackboxes.anno.json | FileCheck %s -check-prefixes=CHECK,SITEST_NODUT
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; RUN: firtool %s -disable-all-randomization -disable-opt -annotation-file %s.sitestblackboxes.anno.json -annotation-file %s.markdut.anno.json | FileCheck %s -check-prefixes=CHECK,SITEST_DUT
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; RUN: firtool %s -repl-seq-mem -repl-seq-mem-file=mems.conf -disable-all-randomization -disable-opt | FileCheck %s -check-prefixes=CHECK,MEMS_NODUT
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; RUN: firtool %s -repl-seq-mem -repl-seq-mem-file=mems.conf -disable-all-randomization -disable-opt -annotation-file %s.markdut.anno.json | FileCheck %s -check-prefixes=CHECK,MEMS_DUT
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; RUN: firtool %s -disable-all-randomization -disable-opt -annotation-file %s.memtoregofvec.anno.json | FileCheck %s -check-prefixes=CHECK,MEMTOREG_NODUT
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; RUN: firtool %s -disable-all-randomization -disable-opt -annotation-file %s.memtoregofvec.anno.json -annotation-file %s.markdut.anno.json | FileCheck %s -check-prefixes=CHECK,MEMTOREG_DUT
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; RUN: firtool %s -disable-all-randomization -disable-opt -repl-seq-mem -repl-seq-mem-file=mems.conf -annotation-file %s.sitestblackboxes.anno.json --ir-verilog | FileCheck %s -check-prefix=MLIR_OUT
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FIRRTL version 4.0.0
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circuit TestHarness:
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; Foo* are instantiated only by the TestHarness
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module Foo:
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mem foo_m :
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data-type => UInt<8>
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depth => 1
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reader => r
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writer => w
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read-latency => 1
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write-latency => 1
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read-under-write => undefined
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mem foo_combmem :
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data-type => UInt<8>
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depth => 1
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reader => r
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writer => w
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read-latency => 0
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write-latency => 1
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read-under-write => undefined
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invalidate foo_m
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invalidate foo_combmem
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extmodule Foo_BlackBox:
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defname = Foo_BlackBox
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; Bar* are instantiated only by the DUT
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module Bar:
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mem bar_m :
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data-type => UInt<8>
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depth => 2
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reader => r
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writer => w
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read-latency => 1
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write-latency => 1
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read-under-write => undefined
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mem bar_combmem :
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data-type => UInt<8>
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depth => 2
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reader => r
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writer => w
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read-latency => 0
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write-latency => 1
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read-under-write => undefined
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invalidate bar_m
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invalidate bar_combmem
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extmodule Bar_BlackBox:
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defname = Bar_BlackBox
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; Baz* are instantiated by both the TestHarness and the DUT
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module Baz:
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mem baz_m :
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data-type => UInt<8>
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depth => 3
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reader => r
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writer => w
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read-latency => 1
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write-latency => 1
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read-under-write => undefined
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mem baz_combmem :
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data-type => UInt<8>
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depth => 3
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reader => r
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writer => w
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read-latency => 0
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write-latency => 1
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read-under-write => undefined
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invalidate baz_m
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invalidate baz_combmem
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extmodule Baz_BlackBox:
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defname = Baz_BlackBox
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; This is the design-under-test. This is marked as such by a separate,
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; optional annotation file.
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module DUT:
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inst bar of Bar
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inst bar_bbox of Bar_BlackBox
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inst baz of Baz
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inst baz_bbox of Baz_BlackBox
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; This is the Test Harness, i.e., the top of the design.
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public module TestHarness:
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inst foo of Foo
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inst foo_bbox of Foo_BlackBox
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inst dut of DUT
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inst baz of Baz
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inst baz_bbox of Baz_BlackBox
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; CHECK: module Foo()
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; MEMTOREG_DUT-NOT: reg [7:0] foo_combmem
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; MEMTOREG_NODUT: reg [7:0] foo_combmem
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; CHECK: endmodule
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; CHECK: module Bar()
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; MEMTOREG_DUT: reg [7:0] bar_combmem
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; MEMTOREG_NODUT: reg [7:0] bar_combmem
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; CHECK: endmodule
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; CHECK: module Baz()
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; MEMTOREG_DUT: reg [7:0] baz_combmem
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; MEMTOREG_NODUT: reg [7:0] baz_combmem
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; CHECK: endmodule
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; SITEST_DUT: FILE "testbench.sitest.json"
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; SITEST_DUT-NOT: FILE
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; SITEST_DUT: "Foo_BlackBox"
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; SITEST_DUT: FILE "design.sitest.json"
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; SITEST_DUT-NOT: FILE
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; SITEST_DUT-DAG: "Bar_BlackBox",
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; SITEST_DUT-DAG: "Baz_BlackBox"
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; SITEST_NODUT: FILE "testbench.sitest.json"
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; SITEST_NODUT-NOT: FILE
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; MLIR_OUT: om.class @SitestBlackBoxModulesSchema(%basepath: !om.basepath, %moduleName_in: !om.string) -> (moduleName: !om.string) {
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; MLIR_OUT: om.class.fields %moduleName_in : !om.string
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; MLIR_OUT: }
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; MLIR_OUT: om.class @SitestBlackBoxMetadata(%basepath: !om.basepath) -> [[V1:.+]]: !om.class.type<@SitestBlackBoxModulesSchema>, [[V2:.+]]: !om.class.type<@SitestBlackBoxModulesSchema>, [[V3:.+]]: !om.class.type<@SitestBlackBoxModulesSchema>
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; MLIR_OUT: %0 = om.constant "Foo_BlackBox" : !om.string
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; MLIR_OUT: %1 = om.object @SitestBlackBoxModulesSchema(%basepath, %0) : (!om.basepath, !om.string) -> !om.class.type<@SitestBlackBoxModulesSchema>
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; MLIR_OUT: %2 = om.constant "Bar_BlackBox" : !om.string
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; MLIR_OUT: %3 = om.object @SitestBlackBoxModulesSchema(%basepath, %2) : (!om.basepath, !om.string) -> !om.class.type<@SitestBlackBoxModulesSchema>
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; MLIR_OUT: %4 = om.constant "Baz_BlackBox" : !om.string
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; MLIR_OUT: %5 = om.object @SitestBlackBoxModulesSchema(%basepath, %4) : (!om.basepath, !om.string) -> !om.class.type<@SitestBlackBoxModulesSchema>
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; MLIR_OUT: om.class.fields %1, %3, %5 : !om.class.type<@SitestBlackBoxModulesSchema>, !om.class.type<@SitestBlackBoxModulesSchema>, !om.class.type<@SitestBlackBoxModulesSchema>
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; MLIR_OUT: }
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; MLIR_OUT: om.class @MemorySchema(%basepath: !om.basepath, %name_in: !om.string, %depth_in: !om.integer, %width_in: !om.integer, %maskBits_in: !om.integer, %readPorts_in: !om.integer, %writePorts_in: !om.integer, %readwritePorts_in: !om.integer, %writeLatency_in: !om.integer, %readLatency_in: !om.integer, %hierarchy_in: !om.list<!om.path>, %inDut_in: i1, %extraPorts_in: !om.list<!om.class.type<@ExtraPortsMemorySchema>>, %preExtInstName_in: !om.list<!om.string>) -> (name: !om.string, depth: !om.integer, width: !om.integer, maskBits: !om.integer, readPorts: !om.integer, writePorts: !om.integer, readwritePorts: !om.integer, writeLatency: !om.integer, readLatency: !om.integer, hierarchy: !om.list<!om.path>, inDut: i1, extraPorts: !om.list<!om.class.type<@ExtraPortsMemorySchema>>, preExtInstName: !om.list<!om.string>)
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; MLIR_OUT: om.class.fields %name_in, %depth_in, %width_in, %maskBits_in, %readPorts_in, %writePorts_in, %readwritePorts_in, %writeLatency_in, %readLatency_in, %hierarchy_in, %inDut_in, %extraPorts_in, %preExtInstName_in : !om.string, !om.integer, !om.integer, !om.integer, !om.integer, !om.integer, !om.integer, !om.integer, !om.integer, !om.list<!om.path>, i1, !om.list<!om.class.type<@ExtraPortsMemorySchema>>, !om.list<!om.string>
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; MLIR_OUT: om.class @MemoryMetadata(%basepath: !om.basepath) -> (foo_m_ext_field: !om.class.type<@MemorySchema>, bar_m_ext_field: !om.class.type<@MemorySchema>, baz_m_ext_field: !om.class.type<@MemorySchema>)
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; MLIR_OUT: om.path_create instance %basepath @memNLA
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; MLIR_OUT: om.list_create
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; MLIR_OUT: om.object @MemorySchema
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; MLIR_OUT: om.constant "foo_m_ext" : !om.string
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; MLIR_OUT: om.constant #om.integer<1 : ui64> : !om.integer
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; MLIR_OUT: om.constant #om.integer<8 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<1 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<1 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<1 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<0 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<1 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<1 : ui32> : !om.integer
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; MLIR_OUT: om.path_create instance %basepath @memNLA_0
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; MLIR_OUT: om.list_create
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; MLIR_OUT: om.object @MemorySchema
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; MLIR_OUT: om.constant "bar_m_ext" : !om.string
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; MLIR_OUT: om.constant #om.integer<2 : ui64> : !om.integer
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; MLIR_OUT: om.constant #om.integer<8 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<1 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<1 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<1 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<0 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<1 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<1 : ui32> : !om.integer
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; MLIR_OUT: om.path_create instance %basepath @memNLA_1
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; MLIR_OUT: om.path_create instance %basepath @memNLA_2
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; MLIR_OUT: om.list_create
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; MLIR_OUT: om.object @MemorySchema
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; MLIR_OUT: om.constant "baz_m_ext" : !om.string
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; MLIR_OUT: om.constant #om.integer<3 : ui64> : !om.integer
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; MLIR_OUT: om.constant #om.integer<8 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<1 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<1 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<1 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<0 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<1 : ui32> : !om.integer
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; MLIR_OUT: om.constant #om.integer<1 : ui32> : !om.integer
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; MLIR_OUT: om.class.fields %4, %20, %38 : !om.class.type<@MemorySchema>, !om.class.type<@MemorySchema>, !om.class.type<@MemorySchema>
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; SITEST_NODUT: FILE "design.sitest.json"
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; SITEST_NODUT-NOT: FILE
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; SITEST_NODUT-DAG: "Foo_BlackBox"
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; SITEST_NODUT-DAG: "Bar_BlackBox"{{,?}}
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; SITEST_NODUT-DAG: "Baz_BlackBox"{{,?}}
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; MEMS_DUT: FILE "metadata{{[/\]}}seq_mems.json"
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; MEMS_DUT-NOT: FILE
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; MEMS_DUT-DAG: "DUT.bar.bar_m.bar_m_ext"
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; MEMS_DUT-DAG: "DUT.baz.baz_m.baz_m_ext"
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; MEMS_NODUT: FILE "metadata{{[/\]}}seq_mems.json"
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; MEMS_NODUT-NOT: FILE
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; MEMS_NODUT-DAG: "TestHarness.foo.foo_m.foo_m_ext"
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; MEMS_NODUT-DAG: "TestHarness.dut.bar.bar_m.bar_m_ext"
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; MEMS_NODUT-DAG: "TestHarness.dut.baz.baz_m.baz_m_ext"
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; MEMS_NODUT-DAG: "TestHarness.baz.baz_m.baz_m_ext"
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