mirror of https://github.com/llvm/circt.git
33 lines
937 B
Plaintext
33 lines
937 B
Plaintext
; RUN: firtool --verilog %s --verify-diagnostics --split-input-file
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; Test tapping a bundle with flips, sink also has flips.
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; Tap sink must be passive.
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FIRRTL version 4.0.0
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circuit Top : %[[
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{
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"class": "sifive.enterprise.grandcentral.DataTapsAnnotation",
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"keys": [
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{
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"class": "sifive.enterprise.grandcentral.ReferenceDataTapKey",
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"source": "~Top|Top/c:Child>x",
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"sink": "~Top|Top>sink"
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}
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]
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}
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]]
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module Child :
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input x: {a : UInt<2>, flip b: UInt<2>}
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connect x.b, UInt<2>(2)
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public module Top :
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input x: {a : UInt<2>, flip b: UInt<2>}
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output tap : {a : UInt<2>, flip b: UInt<2>}
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inst c of Child
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connect c.x, x
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; expected-error @below {{Wiring Problem sink type "'!firrtl.bundle<a: uint<2>, b flip: uint<2>>'" must be passive (no flips) when using references}}
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wire sink : {a : UInt<2>, flip b: UInt<2>}
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invalidate sink
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connect tap, sink
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