mirror of https://github.com/llvm/circt.git
177 lines
4.0 KiB
Plaintext
177 lines
4.0 KiB
Plaintext
; RUN: firtool %s --split-input-file -verify-diagnostics
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FIRRTL version 4.0.0
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circuit TapBetweenWhens : %[[
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{
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"class":"sifive.enterprise.grandcentral.DataTapsAnnotation",
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"keys":[
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{
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"class":"sifive.enterprise.grandcentral.ReferenceDataTapKey",
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"source":"~TapBetweenWhens|TapBetweenWhens>val",
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"sink":"~TapBetweenWhens|TapBetweenWhens>tap"
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}
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]
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}
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]]
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public module TapBetweenWhens :
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input c1: UInt<1>
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input c2: UInt<1>
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output o: UInt<1>
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when c1:
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; expected-error @below {{This value is involved with a Wiring Problem where the destination}}
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wire val : UInt<3>
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connect val, UInt(1)
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invalidate o
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when c2:
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; expected-note @below {{The destination is here.}}
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wire tap: UInt<3>
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invalidate tap
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connect o, tap
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; // -----
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FIRRTL version 4.0.0
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circuit NoSafeInsertionPoint : %[[
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{
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"class":"sifive.enterprise.grandcentral.DataTapsAnnotation",
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"keys":[
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{
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"class":"sifive.enterprise.grandcentral.ReferenceDataTapKey",
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"source":"~NoSafeInsertionPoint|NoSafeInsertionPoint>val",
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"sink":"~NoSafeInsertionPoint|NoSafeInsertionPoint>tap"
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}
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]
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}
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]]
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public module NoSafeInsertionPoint :
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input c: UInt<1>
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output o: UInt<1>
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when c:
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; expected-error @below {{This value is involved with a Wiring Problem where the destination}}
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wire val : UInt<3>
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connect val, UInt(1)
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; expected-note @below {{The destination is here.}}
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wire tap: UInt<3>
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invalidate tap
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connect o, tap
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; // -----
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FIRRTL version 4.0.0
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; expected-error @below {{Unable to apply annotation}}
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circuit Top : %[[
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{
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"class": "firrtl.passes.wiring.SinkAnnotation",
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"target": "Top.BlackBox.sink",
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"pin": "test_pin"
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},
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{
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"class": "firrtl.passes.wiring.SourceAnnotation",
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"target": "Top.Top.legacy_tap",
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"pin": "test_pin"
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},
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{
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"class": "sifive.enterprise.grandcentral.DataTapsAnnotation",
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"keys": [
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{
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"class": "sifive.enterprise.grandcentral.ReferenceDataTapKey",
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"source": "~Top|Top/foo:Foo/b:Bar>inv",
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"sink": "~Top|Top>tap"
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},
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{
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"class":"sifive.enterprise.grandcentral.DataTapModuleSignalKey",
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"module":"~Top|BlackBox",
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"internalPath":"random.something",
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"sink": "~Top|Top>tap2"
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},
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{
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"class":"sifive.enterprise.grandcentral.DataTapModuleSignalKey",
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"module":"~Top|BlackBox",
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"internalPath":"random.something_else",
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"sink": "~Top|Top>tap3"
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},
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{
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"class":"sifive.enterprise.grandcentral.DataTapModuleSignalKey",
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"module":"~Top|InternalPathChild",
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"internalPath":"io_out",
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"sink": "~Top|Top/unsigned:ChildWrapper/signed:Child>tap"
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}
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]
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},
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{
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"class": "firrtl.transforms.DontTouchAnnotation",
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"target": "~Top|Top>tap"
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},
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{
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"class": "firrtl.transforms.DontTouchAnnotation",
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"target": "~Top|Top>tap2"
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},
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{
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"class": "firrtl.transforms.DontTouchAnnotation",
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"target": "~Top|Top>tap3"
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},
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{
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"class": "firrtl.transforms.DontTouchAnnotation",
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"target": "~Top|Child>tap"
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},
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{
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"class": "firrtl.transforms.DontTouchAnnotation",
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"target": "~Top|Bar>inv"
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}
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]]
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module InternalPathChild :
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skip
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; expected-error @below {{'firrtl.extmodule' op cannot be used for both legacy Wiring and DataTaps simultaneously}}
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extmodule BlackBox :
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input sink : UInt<1>
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defname = BlackBox
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module Child :
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inst localparam of BlackBox
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invalidate localparam.sink
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wire tap : UInt<1>
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invalidate tap
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module ChildWrapper :
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inst signed of Child
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module Bar :
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wire inv : UInt<1>
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invalidate inv
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module Foo :
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inst b of Bar
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public module Top:
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inst foo of Foo
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wire tap : UInt<1>
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invalidate tap
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wire tap2 : UInt<1>
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invalidate tap2
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wire tap3 : UInt<1>
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invalidate tap3
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wire legacy_tap : UInt<1>
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invalidate legacy_tap
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inst unsigned of ChildWrapper
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inst int of InternalPathChild
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