mirror of https://github.com/llvm/circt.git
28 lines
664 B
Plaintext
28 lines
664 B
Plaintext
; RUN: firtool --verilog %s | FileCheck %s
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FIRRTL version 4.0.0
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circuit ConstantSinking : %[[
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{
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"class": "sifive.enterprise.grandcentral.DataTapsAnnotation",
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"keys": [
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{
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"class": "sifive.enterprise.grandcentral.ReferenceDataTapKey",
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"source": "~ConstantSinking|ConstantSinking>w",
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"sink": "~ConstantSinking|ConstantSinking>t"
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}
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]
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~ConstantSinking|ConstantSinking>t"
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}
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]]
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public module ConstantSinking:
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output out : UInt<1>
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wire t : UInt<1>
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connect out, t
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invalidate t
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node w = UInt<1>(1)
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; CHECK: wire t = 1'h1;
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