mirror of https://github.com/llvm/circt.git
126 lines
4.5 KiB
Plaintext
126 lines
4.5 KiB
Plaintext
; UNSUPPORTED: system-windows
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; See https://github.com/llvm/circt/issues/4128
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; RUN: rm -rf %t
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; RUN: firtool --repl-seq-mem --repl-seq-mem-file=mems.conf --split-verilog -o=%t %s
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; RUN: FileCheck %s --check-prefix=TESTHARNESS < %t/TestHarness.sv
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; RUN: FileCheck %s --check-prefix=DUTMODULE < %t/DUTModule.sv
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; RUN: FileCheck %s --check-prefix=SEQMEMSGROUP < %t/SeqMemsGroup.sv
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; RUN: FileCheck %s --check-prefix=INJECTEDSUBMODULE < %t/InjectedSubmodule.sv
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; RUN: FileCheck %s --check-prefix=SOMEMODULE < %t/SomeModule.sv
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; RUN: FileCheck %s --check-prefix=MEM < %t/mem.sv
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; RUN: FileCheck %s --check-prefix=MEMS-CONF < %t/mems.conf
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; RUN: FileCheck %s --check-prefix=SEQMEMS-TXT < %t/SeqMems.txt
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; Extracted from test/scala/firrtl/ExtractSeqMems.scala
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; Checks that instance extraction composes with:
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; - Dedup
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; - Inject DUT Hierarchy
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FIRRTL version 4.0.0
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circuit TestHarness : %[[
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{
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"class":"sifive.enterprise.firrtl.InjectDUTHierarchyAnnotation",
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"name":"InjectedSubmodule"
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},
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{
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"class":"sifive.enterprise.firrtl.ExtractSeqMemsFileAnnotation",
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"filename":"SeqMems.txt",
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"group":"SeqMemsGroup"
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},
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{
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"class":"sifive.enterprise.firrtl.MarkDUTAnnotation",
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"target":"TestHarness.DUTModule"
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}
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]]
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module SomeModule :
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input clock : Clock
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input reset : Reset
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output io : { flip addr : UInt<3>, flip dataIn : UInt<8>, flip wen : UInt<1>, dataOut : UInt<8>}
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smem mem : UInt<8> [8]
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infer mport read = mem[io.addr], clock
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connect io.dataOut, read
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when io.wen :
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infer mport write = mem[io.addr], clock
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connect write, io.dataIn
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module SomeModule_1 :
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input clock : Clock
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input reset : Reset
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output io : { flip addr : UInt<3>, flip dataIn : UInt<8>, flip wen : UInt<1>, dataOut : UInt<8>}
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smem mem : UInt<8> [8]
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infer mport read = mem[io.addr], clock
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connect io.dataOut, read
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when io.wen :
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infer mport write = mem[io.addr], clock
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connect write, io.dataIn
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; DUTMODULE: module DUTModule
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; DUTMODULE: SeqMemsGroup SeqMemsGroup
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; DUTMODULE: InjectedSubmodule InjectedSubmodule
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; NOTE(fschuiki): The above should actually read `SeqMemsGroup`, but it
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; is not yet totally clear how to properly order the FIRRTL passes such that
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; the module generated by `ExtractInstances` gets properly prefixed.
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module DUTModule :
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input clock : Clock
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input reset : Reset
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output io : { foo : { flip addr : UInt<3>, flip dataIn : UInt<8>, flip wen : UInt<1>, dataOut : UInt<8>}, bar : { flip addr : UInt<3>, flip dataIn : UInt<8>, flip wen : UInt<1>, dataOut : UInt<8>}}
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inst inst0 of SomeModule
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connect inst0.clock, clock
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connect inst0.reset, reset
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connect io.foo.dataOut, inst0.io.dataOut
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connect inst0.io.wen, io.foo.wen
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connect inst0.io.dataIn, io.foo.dataIn
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connect inst0.io.addr, io.foo.addr
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inst inst1 of SomeModule_1
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connect inst1.clock, clock
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connect inst1.reset, reset
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connect io.bar.dataOut, inst1.io.dataOut
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connect inst1.io.wen, io.bar.wen
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connect inst1.io.dataIn, io.bar.dataIn
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connect inst1.io.addr, io.bar.addr
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; TESTHARNESS: module TestHarness
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; TESTHARNESS: DUTModule dut
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; TESTHARNESS-NOT: mem_ext mem_ext
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; TESTHARNESS-NOT: mem_ext mem_ext
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public module TestHarness :
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input clock : Clock
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input reset : UInt<1>
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output io : { foo : { flip addr : UInt<3>, flip dataIn : UInt<8>, flip wen : UInt<1>, dataOut : UInt<8>}, bar : { flip addr : UInt<3>, flip dataIn : UInt<8>, flip wen : UInt<1>, dataOut : UInt<8>}}
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inst dut of DUTModule
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connect dut.clock, clock
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connect dut.reset, reset
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connect io.bar.dataOut, dut.io.bar.dataOut
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connect dut.io.bar.wen, io.bar.wen
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connect dut.io.bar.dataIn, io.bar.dataIn
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connect dut.io.bar.addr, io.bar.addr
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connect io.foo.dataOut, dut.io.foo.dataOut
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connect dut.io.foo.wen, io.foo.wen
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connect dut.io.foo.dataIn, io.foo.dataIn
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connect dut.io.foo.addr, io.foo.addr
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; INJECTEDSUBMODULE: module InjectedSubmodule
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; INJECTEDSUBMODULE: SomeModule inst0
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; INJECTEDSUBMODULE: SomeModule inst1
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; SOMEMODULE: module SomeModule
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; SOMEMODULE: mem mem
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; SEQMEMSGROUP: module SeqMemsGroup
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; SEQMEMSGROUP: mem_wiring_1_R0_addr
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; SEQMEMSGROUP: mem_wiring_0_R0_addr
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; SEQMEMSGROUP: mem_ext mem_ext
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; SEQMEMSGROUP: mem_ext mem_ext
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; MEM: module mem
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; MEM-NOT: mem_ext mem_ext
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; MEM-NOT: mem_ext mem_ext
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; MEMS-CONF: name mem_ext depth 8 width 8 ports write,read
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; SEQMEMS-TXT: mem_wiring_1 -> DUTModule.InjectedSubmodule.inst0.mem
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; SEQMEMS-TXT: mem_wiring_0 -> DUTModule.InjectedSubmodule.inst1.mem
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