mirror of https://github.com/llvm/circt.git
26 lines
721 B
MLIR
26 lines
721 B
MLIR
// RUN: circt-opt -export-verilog -verify-diagnostics --split-input-file -mlir-print-op-on-diagnostic=false %s
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// expected-error @+1 {{value has an unsupported verilog type 'f32'}}
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hw.module @Top(in %out: f32) {
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}
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// -----
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// expected-error @+2 {{unknown style option 'badOption'}}
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// expected-error @+1 {{unknown style option 'anotherOne'}}
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module attributes {circt.loweringOptions = "badOption,anotherOne"} {}
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// -----
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hw.module.extern @A<width: none> ()
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hw.module @B() {
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// expected-error @+1 {{should have a typed value; has value @Foo}}
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hw.instance "foo" @A<width: none = @Foo>() -> ()
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}
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// -----
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// expected-error @+1 {{name "parameter" is not allowed in Verilog output}}
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hw.module.extern @parameter ()
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