mirror of https://github.com/llvm/circt.git
92 lines
3.2 KiB
MLIR
92 lines
3.2 KiB
MLIR
// RUN: circt-opt %s -prettify-verilog --export-verilog --verify-diagnostics -o %t | FileCheck %s --strict-whitespace
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// RUN: circt-opt %s -test-apply-lowering-options='options=exprInEventControl' -prettify-verilog -export-verilog | FileCheck %s --check-prefix=INLINE
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// CHECK-LABEL: module AlwaysSpill(
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hw.module @AlwaysSpill(in %port: i1) {
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%false = hw.constant false
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%true = hw.constant true
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%awire = sv.wire : !hw.inout<i1>
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// CHECK: wire [[TMP1:.+]] = 1'h0;
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// CHECK: wire [[TMP2:.+]] = 1'h1;
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// CHECK: wire{{ *}}awire;
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%awire2 = sv.read_inout %awire : !hw.inout<i1>
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// Existing simple names should not cause additional spill.
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// CHECK: always @(posedge port)
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sv.always posedge %port {}
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// CHECK: always_ff @(posedge port)
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sv.alwaysff(posedge %port) {}
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// CHECK: always @(posedge awire)
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sv.always posedge %awire2 {}
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// CHECK: always_ff @(posedge awire)
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sv.alwaysff(posedge %awire2) {}
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// Constant values should cause a spill.
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// CHECK: always @(posedge [[TMP1]])
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// INLINE: always @(posedge 1'h0)
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sv.always posedge %false {}
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// CHECK: always_ff @(posedge [[TMP2]])
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// INLINE: always_ff @(posedge 1'h1)
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sv.alwaysff(posedge %true) {}
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}
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// CHECK-LABEL: module Foo
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// INLINE-LABEL: module Foo
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hw.module @Foo(in %reset0: i1, in %reset1: i1) {
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%0 = comb.or %reset0, %reset1 : i1
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// CHECK: wire [[TMP0:.*]] = reset0 | reset1;
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// CHECK-NEXT: always @(posedge [[TMP0]])
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// CHECK-NEXT: if ([[TMP0]])
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sv.always posedge %0 {
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sv.if %0 {
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}
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}
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%true = hw.constant true
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%1 = comb.xor %reset0, %true : i1
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// CHECK: wire [[TMP1:.*]] = ~reset0;
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// CHECK-NEXT: always @(posedge [[TMP1]])
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// CHECK-NEXT: if ([[TMP1]])
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// INLINE: always @(posedge ~reset0)
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// INLINE-NEXT: if (~reset0)
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sv.always posedge %1 {
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sv.if %1 {
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}
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}
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// CHECK: assert property (@(posedge [[TMP1]]) [[TMP1]]);
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// INLINE: assert property (@(posedge ~reset0) ~reset0);
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sv.assert.concurrent posedge %1, %1
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// CHECK-NEXT: assume property (@(posedge [[TMP1]]) [[TMP1]]);
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// INLINE-NEXT: assume property (@(posedge ~reset0) ~reset0);
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sv.assume.concurrent posedge %1, %1
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// CHECK-NEXT: cover property (@(posedge [[TMP1]]) [[TMP1]]);
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// INLINE-NEXT: cover property (@(posedge ~reset0) ~reset0);
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sv.cover.concurrent posedge %1, %1
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}
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// CHECK-LABEL: ClockedAsserts
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// INLINE-LABEL: ClockedAsserts
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hw.module @ClockedAsserts(in %clk: i1, in %a: i1, in %b: i1) {
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%true = hw.constant true
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%n0 = ltl.not %a : i1
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%1 = comb.xor %clk, %true : i1
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%2 = comb.xor %a, %true : i1
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// CHECK: wire [[TMP0:_.+]] = ~clk;
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// CHECK-NEXT: wire [[TMP1:_.+]] = ~a;
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// CHECK: assert property (@(posedge [[TMP0]]) disable iff ([[TMP1]]) not a);
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// INLINE: assert property (@(posedge ~clk) disable iff (~a) not a);
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sv.assert_property %n0 on posedge %1 disable_iff %2 : !ltl.property
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// CHECK-NEXT: assume property (@(posedge [[TMP0]]) disable iff ([[TMP1]]) not a);
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// INLINE-NEXT: assume property (@(posedge ~clk) disable iff (~a) not a);
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sv.assume_property %n0 on posedge %1 disable_iff %2 : !ltl.property
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// CHECK-NEXT: cover property (@(posedge [[TMP0]]) disable iff ([[TMP1]]) not a);
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// INLINE-NEXT: cover property (@(posedge ~clk) disable iff (~a) not a);
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sv.cover_property %n0 on posedge %1 disable_iff %2: !ltl.property
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}
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