mirror of https://github.com/llvm/circt.git
62 lines
2.7 KiB
MLIR
62 lines
2.7 KiB
MLIR
// RUN: circt-opt -export-verilog --split-input-file %s | FileCheck %s
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// RUN: circt-opt -test-apply-lowering-options='options=emittedLineLength=10' -export-verilog --split-input-file %s | FileCheck %s
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// https://github.com/llvm/circt/issues/4181
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// CHECK{LITERAL}: // {{
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// CHECK-NEXT: endmodule
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hw.module @VerbatimWrapping(in %clock : i1, in %cond : i1, in %val : i8, in %a : i3, in %b : i3) {
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%x = comb.add %a, %b : i3
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%y = comb.xor %a, %b : i3
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%arr = hw.array_create %x, %y, %x, %y, %x, %y, %x, %y, %x, %y, %x, %y : i3
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sv.verbatim "// {{0}}" (%arr) : !hw.array<12xi3>
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}
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// -----
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// https://github.com/llvm/circt/issues/4182
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// CHECK-LABEL: TestZero(
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// CHECK: input /*Zero Width*/ zeroBitWithAVeryLongNameWhichMightSeemUnlikelyButHappensAllTheTime
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// CHECK-NEXT: input [2:0]/*Zero Width*/ arrZero
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// CHECK: // Zero width: assign rZeroOutputWithAVeryLongName_YepThisToo_LongNamesAreTheWay_MoreText_GoGoGoGoGo
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// CHECK-SAME: ;
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// CHECK-NEXT: // Zero width: assign
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// CHECK-SAME: ;
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// CHECK-NEXT: endmodule
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hw.module @TestZero(in %a: i4, in %zeroBitWithAVeryLongNameWhichMightSeemUnlikelyButHappensAllTheTime: i0, in %arrZero: !hw.array<3xi0>,
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out r0: i4, out rZeroOutputWithAVeryLongName_YepThisToo_LongNamesAreTheWay_MoreText_GoGoGoGoGo: i0, out arrZero_0: !hw.array<3xi0>) {
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%b = comb.add %a, %a : i4
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%c = comb.add %zeroBitWithAVeryLongNameWhichMightSeemUnlikelyButHappensAllTheTime, %zeroBitWithAVeryLongNameWhichMightSeemUnlikelyButHappensAllTheTime : i0
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hw.output %b, %c, %arrZero : i4, i0, !hw.array<3xi0>
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}
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// Module ports:
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// CHECK-LABEL: TestZeroInstance(
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// CHECK: // input /*Zero Width*/ azeroBit
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// CHECK-NEXT: // input [2:0]/*Zero Width*/ aarrZero
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// CHECK: // output /*Zero Width*/ rZeroOutputWithAVeryLongNameYepThisToo
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// Wire:
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// CHECK: // Zero width: wire /*Zero Width*/ [[ZERO_WIRE:.+]];
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// Instance ports:
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// CHECK: //.zeroBitWithAVeryLongNameWhichMightSeemUnlikelyButHappensAllTheTime (azeroBit),
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// CHECK: //.rZeroOutputWithAVeryLongName_YepThisToo_LongNamesAreTheWay_MoreText_GoGoGoGoGo ([[ZERO_WIRE]])
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// Output:
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// CHECK: // Zero width: assign
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// CHECK-SAME: ;
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// CHECK-NEXT: endmodule
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hw.module @TestZeroInstance(in %aa: i4, in %azeroBit: i0, in %aarrZero: !hw.array<3xi0>,
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out r0: i4, out rZeroOutputWithAVeryLongNameYepThisToo: i0, out arrZero_0: !hw.array<3xi0>) {
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%o1, %o2, %o3 = hw.instance "iii" @TestZero(a: %aa: i4, zeroBitWithAVeryLongNameWhichMightSeemUnlikelyButHappensAllTheTime: %azeroBit: i0, arrZero: %aarrZero: !hw.array<3xi0>) -> (r0: i4, rZeroOutputWithAVeryLongName_YepThisToo_LongNamesAreTheWay_MoreText_GoGoGoGoGo: i0, arrZero_0: !hw.array<3xi0>)
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%c = comb.add %o2, %o2 : i0
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hw.output %o1, %c, %o3 : i4, i0, !hw.array<3xi0>
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}
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