mirror of https://github.com/llvm/circt.git
24 lines
939 B
MLIR
24 lines
939 B
MLIR
// RUN: circt-opt -pass-pipeline='builtin.module(calyx.component(materialize-calyx-to-fsm))' -split-input-file -verify-diagnostics %s
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calyx.component @main(%go: i1 {go}, %reset: i1 {reset}, %clk: i1 {clk}) -> (%done: i1 {done}) {
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%r.in, %r.write_en, %r.clk, %r.reset, %r.out, %r.done = calyx.register @r : i32, i1, i1, i1, i32, i1
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calyx.wires {
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calyx.assign %r.clk = %clk : i1
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}
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// expected-error @+1 {{'calyx.control' op expected an 'fsm.machine' operation as the top-level operation within the control region of this component.}}
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calyx.control {
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calyx.seq {}
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}
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}
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// -----
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calyx.component @main(%go: i1 {go}, %reset: i1 {reset}, %clk: i1 {clk}) -> (%done: i1 {done}) {
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calyx.wires {
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}
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calyx.control {
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// expected-error @+1 {{'fsm.machine' op Expected an 'fsm_entry' and 'fsm_exit' state to be present in the FSM.}}
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fsm.machine @control() attributes {initialState = "IDLE"} {
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fsm.state @IDLE
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}
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}
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}
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