mirror of https://github.com/llvm/circt.git
119 lines
4.4 KiB
MLIR
119 lines
4.4 KiB
MLIR
// RUN: circt-opt --split-input-file -pass-pipeline='builtin.module(calyx.component(lower-calyx-to-fsm))' %s | FileCheck %s
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// CHECK: fsm.machine @control_main()
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// CHECK-NEXT: fsm.state @fsm_entry output {
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// CHECK-NEXT: fsm.output
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// CHECK-NEXT: } transitions {
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// CHECK-NEXT: fsm.transition @seq_0_cond
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// CHECK-NEXT: }
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// CHECK-NEXT: fsm.state @fsm_exit output {
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// CHECK-NEXT: fsm.output
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// CHECK-NEXT: } transitions {
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// CHECK-NEXT: }
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// CHECK-NEXT: fsm.state @seq_1_while_header output {
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// CHECK-NEXT: fsm.output
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// CHECK-NEXT: } transitions {
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// CHECK-NEXT: fsm.transition @seq_1_while_if guard {
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// CHECK-NEXT: fsm.return %lt_reg.out
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// CHECK-NEXT: }
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// CHECK-NEXT: fsm.transition @fsm_exit guard {
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// CHECK-NEXT: %true_0 = hw.constant true
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// CHECK-NEXT: %0 = comb.xor %lt_reg.out, %true_0 : i1
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// CHECK-NEXT: fsm.return %0
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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// CHECK-NEXT: fsm.state @seq_1_while_if output {
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// CHECK-NEXT: fsm.output
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// CHECK-NEXT: } transitions {
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// CHECK-NEXT: fsm.transition @seq_1_while_if_then guard {
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// CHECK-NEXT: fsm.return %lt_reg.out
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// CHECK-NEXT: }
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// CHECK-NEXT: fsm.transition @seq_1_while_if_else guard {
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// CHECK-NEXT: %true_0 = hw.constant true
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// CHECK-NEXT: %0 = comb.xor %lt_reg.out, %true_0 : i1
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// CHECK-NEXT: fsm.return %0
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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// CHECK-NEXT: fsm.state @seq_1_while_if_then output {
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// CHECK-NEXT: fsm.output
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// CHECK-NEXT: } transitions {
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// CHECK-NEXT: fsm.transition @seq_1_while_if_then_seq_0_do_add
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// CHECK-NEXT: }
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// CHECK-NEXT: fsm.state @seq_1_while_if_then_seq_1_do_add output {
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// CHECK-NEXT: calyx.enable @do_add
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// CHECK-NEXT: fsm.output
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// CHECK-NEXT: } transitions {
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// CHECK-NEXT: fsm.transition @seq_1_while_header
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// CHECK-NEXT: }
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// CHECK-NEXT: fsm.state @seq_1_while_if_then_seq_0_do_add output {
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// CHECK-NEXT: calyx.enable @do_add
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// CHECK-NEXT: fsm.output
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// CHECK-NEXT: } transitions {
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// CHECK-NEXT: fsm.transition @seq_1_while_if_then_seq_1_do_add
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// CHECK-NEXT: }
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// CHECK-NEXT: fsm.state @seq_1_while_if_else output {
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// CHECK-NEXT: fsm.output
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// CHECK-NEXT: } transitions {
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// CHECK-NEXT: fsm.transition @seq_1_while_if_else_seq_0_do_add
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// CHECK-NEXT: }
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// CHECK-NEXT: fsm.state @seq_1_while_if_else_seq_0_do_add output {
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// CHECK-NEXT: calyx.enable @do_add
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// CHECK-NEXT: fsm.output
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// CHECK-NEXT: } transitions {
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// CHECK-NEXT: fsm.transition @seq_1_while_header
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// CHECK-NEXT: }
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// CHECK-NEXT: fsm.state @seq_0_cond output {
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// CHECK-NEXT: calyx.enable @cond
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// CHECK-NEXT: fsm.output
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// CHECK-NEXT: } transitions {
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// CHECK-NEXT: fsm.transition @seq_1_while_header
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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calyx.component @main(%go: i1 {go}, %reset: i1 {reset}, %clk: i1 {clk}) -> (%done: i1 {done}) {
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%true = hw.constant true
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%c1_i32 = hw.constant 1 : i32
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%c5_i32 = hw.constant 5 : i32
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%c4_i32 = hw.constant 4 : i32
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%lt_reg.in, %lt_reg.write_en, %lt_reg.clk, %lt_reg.reset, %lt_reg.out, %lt_reg.done = calyx.register @lt_reg : i1, i1, i1, i1, i1, i1
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%r.in, %r.write_en, %r.clk, %r.reset, %r.out, %r.done = calyx.register @r : i32, i1, i1, i1, i32, i1
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%add.left, %add.right, %add.out = calyx.std_add @add : i32, i32, i32
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%lt.left, %lt.right, %lt.out = calyx.std_lt @lt : i32, i32, i1
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calyx.wires {
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%0 = calyx.undef : i1
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calyx.group @do_add {
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%do_add.go = calyx.group_go %0 : i1
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calyx.assign %add.right = %do_add.go ? %c4_i32 : i32
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calyx.assign %add.left = %do_add.go ? %c4_i32 : i32
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calyx.assign %r.in = %do_add.go ? %add.out : i32
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calyx.assign %r.write_en = %do_add.go ? %true : i1
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calyx.group_done %r.done : i1
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}
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calyx.group @cond {
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%cond.go = calyx.group_go %0 : i1
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calyx.assign %lt_reg.in = %cond.go ? %lt.out : i1
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calyx.assign %lt_reg.write_en = %cond.go ? %true : i1
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calyx.assign %lt.right = %cond.go ? %c5_i32 : i32
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calyx.assign %lt.left = %cond.go ? %c1_i32 : i32
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calyx.group_done %lt_reg.done ? %true : i1
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}
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}
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calyx.control {
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calyx.seq {
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calyx.enable @cond
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calyx.while %lt_reg.out {
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calyx.if %lt_reg.out {
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calyx.seq {
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calyx.enable @do_add
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calyx.enable @do_add
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}
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} else {
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calyx.seq {
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calyx.enable @do_add
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}
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}
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}
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}
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}
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}
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